Additional Notes 2: In-Depth Notes on Phase-Locked Loop (PLL) Systems

Key Concepts of PLL (Phase-Locked Loop)

• PLL Block Diagram:

  • Consists of a Phase Detector, Loop Filter, and Voltage-Controlled Oscillator (VCO).
  • Key signals: V1(t) = A sin(wt + φ) and V2(t) = B cos(wt + ψ).

• Phase Detector (PD):

  • Acts as a correlator that generates a control signal Vd (E, A$).
  • Proportional to time difference I (phase difference Δφ) between V1 and V2.
  • The equation is given by:
    R(t) = + SV1(t) V2(t + c) \ \alpha t
    A B K M \sin(4-62) = Kd \text{ (gain)} A \sin A \phi.
  • PD Constant:
    K_d = \sqrt{(8 \alpha 4) | A B K M |}

• Loop Filter (LF):

  • Transfer function is given by:
    F(s) = R + \frac{1}{sc}
  • Behavior characterized by zeros and poles affecting loop stability.
  • Ensure that:
  • R1 + R2 >> R2 to achieve 20 dB attenuation in stop-band.
  • Zero at -½/22 and pole at 3 - - ½.

• VCO (Voltage-Controlled Oscillator):

  • Acts as an ideal integrator with gain kw.
  • Transfer function:
    V_{CO}(s) = kw, contributing a pole at f = 0.
  • Generates V2(t) = B cos[wet + kω(V(True) dz)].

• Damping Behavior and Stability in the PLL:

  • Damping constant defined as:
    Damping\ Constant = kd.
  • PLL aims for stable node, tracking frequency correctly when locking occurs.

• Locking Behavior:

  • Notable when input frequency step occurs. The increased loop gain facilitates locking.
  • Phase error representation for stability:
  • Expectation is higher gain reduces $\Delta \phi$ residual error.
  • Mathematically described:
    \Delta \omega < K_t indicating locking condition.

• Analysis of Step Inputs:

  • Frequency step in PLL input leads to tracking and stabilization, plotted on phase-plane.
  • Larger gains yield better response and locking characteristics.

• Key Formulas:

  • Natural angular frequency of PLL:
    \omega_n = K'\text{ (rad/s)} where $K' = K/N$.
  • Noise bandwidth and 3dB bandwidth defined within PLL.
  • Max frequency offset for tracking and pull-in:
    \Delta \omega_{max} = \sqrt{2}[25K' - w^2]
  • Time required for PLL to lock at frequency offset given by:
    T_F = \frac{(4)²}{(250) \Delta \omega²}

• Qualitative Analysis:

  • Explore the output phase error and its relationship with constants A, K1, K2.
  • Consider effects of higher gain on locking and dynamic response as plotted.

• Homework Assignment:

  • Derive expressions for phase errors and develop stability plots including expected results based on found constants.