Page 1: Introduction

SCS3301 Computer Architecture Control Unit Operation

Page 2: Outline

Topics Covered

1. Micro Operations

2. Control Unit Functions

3. Control Unit Implementation

   • Hardwired Implementation

   • Microprogram Implementation

Page 3: Micro-Operations

Definition

• Micro-operations are the atomic operations performed by a processor while executing a program.

• Each instruction cycle has several smaller cycles, including fetch, indirect, execute, and interrupt.

• Fetch and execute cycles occur consistently across instruction cycles.

Detail

• Smaller cycles comprise a series of steps involving processor registers, known as micro-operations.

• Every step is simple and contributes minimally by itself to the overall processing task.

Page 4: Program Execution

Instruction Cycle Components

• Instruction cycles consist of various phases, notably fetch, indirect, execute, and interrupt.

• Each phase involves specific micro-operations (µOP).

Visual Representation

Page 5: The Control Unit

Fundamental Functions

• Processor functions decompose into micro-operations.

• Understanding micro-operations guides defining the control unit's functional requirements.

• These requirements drive the design and implementation of the control unit.

Page 6: Characterization of the Control Unit

Three-Step Process

1. Define the basic elements of the processor.

2. Describe the micro-operations performed by the processor.

3. Determine the necessary functions for the control unit to execute those micro-operations.

Page 7: Basic Functional Elements of the Processor

Core Elements

• ALU: The functional essence of the computer.

• Registers: Store data and status internal to the processor.

• Internal Data Paths: Move data between registers and between registers and the ALU.

• External Data Paths: Link registers to memory and I/O modules, typically using a system bus.

• Control Unit: Manages and orchestrates operations within the processor.

Page 8: Micro-Operations Categories

Execution Activities

• All micro-operations performed by the processor can be categorized into:

  • Transfers between registers.

  • Transfers between a register and external interfaces (e.g., system bus).

  • Arithmetic or logic operations utilizing registers for input and output.

Page 9: Instruction Fetching Cycle

Cycle Steps

• t1: MAR ← (PC)

• t2: MBR ← M(MAR)

• t3: IR ← (MBR)

Registers Involved

• MAR: Memory Address Register

• MBR: Memory Buffer Register

• PC: Program Counter

• IR: Instruction Register

Page 10: The Fetch Cycle

Overview

• Initiates each instruction cycle to retrieve an instruction from memory.

Key Registers

1. Memory Address Register (MAR): Specifies read/write addresses.

2. Memory Buffer Register (MBR): Holds data for read/write operations.

3. Program Counter (PC): Points to the next instruction address.

4. Instruction Register (IR): Stores the most recently fetched instruction.

Page 11: Indirect Addressing Cycle

Cycle Steps

• t1: MAR ← (IR(Address))

• t2: MBR ← M(MAR)

• t3: IR(Address) ← (MBR(Address))

Page 12: Indirect Cycle Overview

Purpose

• Follows instruction fetching to retrieve source operands, especially when indirect addressing is specified.

• Steps involved include:

  1. Load instruction's address into the MAR.

  2. Fetch operand address via MAR.

  3. Update IR to contain a direct address.

Page 13: Interrupt Cycle

Interrupt Cycle Steps

• t1: MBR ← (PC)

• t2: MAR ← Address

• t3: M(MAR) ← (MBR)

Page 14: Interrupt Cycle Execution

Cycle Functionality

• Occurs post-execution cycle upon detection of enabled interrupts.

Steps

1. Save content of the PC in MBR.

2. Load MAR with the address for saving PC's content.

3. Load PC with the address of the interrupt-processing routine.

4. Store MBR back to memory.

Page 15: Execute Cycle (1)

Varied Micro-Operations

• The execution phase varies greatly based on opcode with steps like instruction decoding.

Example: Simplified ADD Instruction

• ADD R1, X:

  • t1: MAR ← (IR(Address))

  • t2: MBR ← (memory)

  • t3: R1 ← R1 + (MBR)

Page 16: Execute Cycle (2)

Sample Complex Operation

• ISZ X – Increment and skip if zero:

  • Executes several micro-operations, such as checking register values and conditionally modifying PC.

Page 17: Execute Cycle (3)

Complex Functionality Example

• BSA X – Branch and save address

  • Stores the next instruction’s address in memory and continues execution from an altered location.

  • Steps include loading MAR with the instruction address and updating the PC.

Page 18: Rules for Micro-Operations Grouping

Important Guidelines

• Proper sequence handling:

  • MAR ← (PC) must precede MBR ← (memory).

• Avoid conflicts:

  • Reading and writing to the same register simultaneously is not allowed.

  • Multiple actions involving ALU must be scheduled correctly to avoid hardware duplication.

Page 19: Instruction Cycle Breakdown

Micro-Operations Structure

• Phases are decomposed into distinct sequences of micro-operations.

Example: BSA X - Requires coordination between fetch and execution sequences.

Page 20: Register Instruction Cycle Code (ICC)

Definition

• A register tracks the instruction cycle code, indicative of the processor’s state, with codes such as:

  • 00 – Fetching

  • 01 – Indirect addressing

  • 10 – Execution

  • 11 – Interrupt

Page 21: Flowchart for Instruction Cycle

ICC Flow Control

• Visual representation guiding instruction processing phases; demonstrates decision-making in handling interrupts and addressing modes.

Page 22: Control Unit Functions

Essential Tasks

1. Sequencing: Orchestrates processor micro-operations sequentially.

2. Execution: Triggers individual micro-operations through control signals.

Page 23: Inputs of the Control Unit

Control Signals

• Clock: Signals operations timing.

• Instruction Register: Holds op-code dictating carried micro-instructions.

• Flags: Indicate CPU state and previous operation results.

Page 24: Outputs of the Control Unit

Control Signals Impact

• Commands for data movement between registers.

• Activation of specific ALU functions.

• Control signals to memory and I/O modules.

Page 25: Block Diagram of the Control Unit

Page 26: Micro-operations and Control Signals

Table of Micro-operations

• Breakdown of active control signals for various steps in instruction execution, detailing function and outcome.

Page 27: Control Unit Implementation

Implementation Types

• Circuit Implementation: Fast but complex and costly.

• Microprogram Implementation: Lower cost, more flexible, widely used in CISC machines.

Page 28: Hardwired Implementation (1)

Definition and Elements

• Inputs include flags and opcode from instruction register; decoders are essential for generating control signals.

Page 29: Hardwired Implementation (2)

Timing Mechanisms

• Detailed clock pulse sequences guide control signal generation corresponding to micro-operations.

Page 30: Hardwired Control Unit Block

Architecture Overview

• Components include instruction registers, decoders, and timing generators reflecting connections and function.

Page 31: Problems with Hardwired Designs

Limitations

• Complexity in design and sequencing.

• Inflexibility to adapt to new instructions.

Page 32: Microprogram Implementation

Overview

• Microprogram details dictate control unit operations; uses control memory to store micro-operations.

• Structured to signal register transfers and ALU operations.

Page 33: Micro-instruction Functionality

Generation of Control Signals

• Control signals active based on present op-code and its conditions; specifies operations through a control word for every micro-operation.

Page 34: Micro-instruction Types

Variants

1. Vertical Micro-Programming: Few operations specified.

2. Horizontal Micro-Programming: Multiple operations executed in parallel.

Page 35: Microinstruction Formats

Typical Forms

• Various formats to represent necessary micro-operations clearly.

Page 36: Operation Overview

Key Components

• Micro-Operations

• Control Unit Functions

• Control Unit Implementation

Page 37: Control Unit Organization

Structure

• Conveys the logical arrangement and relationships among control unit components.

Page 38: Control Unit Functionality

Primary Tasks

• Issues read commands.

• Generates control signals post-read operation based on control buffer register contents.

Page 39: Next Address Decision Process

Address Handling

• Process involves decision-making for the next operation using control address register adjustments based on flag values and control buffer contents.

Page 40: Functionality of Microprogrammed Control Unit

Operational Mechanism

• Details how microprogramming influences the control unit's behavior and efficiency.

• Outlines the sequence and decision-making involved in operations.

Page 41: Advantages and Disadvantages of Microprogramming

Benefits

• Simpler design, cost-effective, reduced error rates.

Drawbacks

• Generally slower than hardwired designs.

Page 42: Summary

Key Points Covered

• Micro-operations definition and types.

• Instruction cycle phases: fetch, indirect, interrupt, execute.

• Control unit functionality and requirements.

• Implementation methods and their implications.

SCS3301 Computer Architecture Control Unit Operation

Overview

• Micro-Operations: Defined as the basic atomic operations that occur during program execution, encompassing key cycles such as fetch, indirect, execute, and interrupt, which together enable the processor to function effectively.

• Control Unit Functions: This unit orchestrates the sequence of micro-operations executed by the processor, which is crucial for understanding both the functional requirements and the design of the control unit itself.

Control Unit Characterization

1. Define Processor Elements: Identifying and outlining the fundamental components that make up the processor, such as the ALU, registers, and buses.

2. Describe Performed Micro-Operations: Analyzing the specific micro-operations that are executed by these elements during instruction processing.

3. Identify Control Unit Functions: Determining the necessary functions that the control unit must perform to enable the execution of the aforementioned micro-operations effectively.

Processor Functional Elements

• ALU (Arithmetic Logic Unit): The processing backbone of the computer that carries out arithmetic and logic operations.

• Registers: Fast storage locations within the processor that hold data and status information temporarily during execution.

• Data Paths: Internal pathways for moving data between registers and the ALU, while external paths connect these internal components to memory and input/output modules.

• Control Unit: The mastermind that manages and coordinates all operations within the processor, ensuring that everything runs in sync.

Instruction Cycle Phases

• Fetch Cycle: The first step where the processor loads an instruction from memory, storing it in the Instruction Register (IR).

• Indirect Addressing Cycle: This occurs when the processor retrieves the operand addresses specified in the instruction, facilitating flexible data access.

• Execute Cycle: The stage where the processor performs the necessary operations as dictated by the instruction's op-code, executing relevant micro-operations.

• Interrupt Cycle: Conducted after the execution phase, this cycle addresses any interrupt signals, ensuring the processor can respond to critical events.

Control Unit Implementation

• Types of Implementation: There are primarily two approaches to implementing control units - Hardwired implementation, known for its speed and complexity; and Microprogrammed implementation, characterized by its flexibility and lower cost.

• Microprogramming: Involves the use of control memory to store the sequences of micro-operations, generating control signals based on the current operation’s op-code; it provides advantages such as a streamlined design but may exhibit slower performance relative to hardwired systems due to additional layers of abstraction.

Summary Points

• Understanding micro-operations is fundamental for grasping the detailed processes involved in the instruction cycle.

• The functions performed by the control unit are essential for governing the operational efficiency of the processor.