The Fetch Stage | The fetch-decode-execute cycle | Ada Computer Science

The Fetch, Decode, Execute Cycle

Overview

The execution of instructions is crucial in how processors operate within a Central Processing Unit (CPU). This is accomplished through a systematic process known as the fetch, decode, execute cycle, which is fundamental for the execution of tasks by the CPU.

1. Fetch Stage

Initiation of Fetch Process:

The process commences when the necessary memory address for data retrieval is prepared. This address is maintained in the Program Counter (PC), which tracks the sequence of instructions.

Memory Address Register (MAR):

Once a memory address is prepared (for instance, address zero in this case), it is conveyed through the address bus to the Memory Address Register (MAR). This register acts as a pointer to the memory location that needs to be accessed.

Data Retrieval from Main Memory:

The MAR reaches out to main memory to retrieve the data residing at the designated memory address. Upon successful access of the main memory, the data present at that address, such as at address zero, is read and transported onto the data bus for further processing.

2. Loading the Data

Transfer to CPU:

Following the data retrieval, it is essential for the retrieved data to be delivered back to the CPU for processing to occur efficiently. This step is pivotal in transitioning between memory and the CPU.

Memory Data Register (MDR):

The data fetched from the main memory is stored in the Memory Data Register (MDR), alternatively known as the Memory Buffer Register (MBR). This register acts as a temporary storage area that holds the data and instructions needed for the CPU to execute the current operations effectively.

Current Instruction Register (CIR):

If the fetched data denotes an instruction (for example, "load two"), it is transferred from the MDR to the Current Instruction Register (CIR) via the data bus. The CIR is critical as it temporarily holds the instruction that the CPU is currently executing, thereby ensuring an orderly processing sequence.

3. Update Program Counter

Increment PC:

The final action of the fetch stage is executed by the Control Unit, which directs the Program Counter to increment its value by one. This update is essential as it prepares the system for the next fetch operation by advancing to the memory address of the subsequent instruction, thereby ensuring a continuous flow of command execution without interruption.