Fetch Decode Execute Cycle & CPU Notes

CPU Components
  • Control Unit (CU)
  • Arithmetic & Logic Unit (ALU)
  • Registers: Program Counter (PC), Memory Address Register (MAR), Memory Data Register (MDR), Current Instruction Register (CIR), Accumulator (ACC)
  • Cache
  • Main Memory (RAM)
  • Input / Output devices
Von Neumann Buses
  • Address Bus\text{Address Bus} – carries memory addresses from MAR to RAM
  • Data Bus\text{Data Bus} – carries data/instructions between CPU and RAM
  • Control Bus\text{Control Bus} – carries control signals (read/​write, clock, interrupt)
Fetch-Decode-Execute (FDE) Cycle – Overview
  • Continuous loop; one instruction handled per cycle
  • Stages: Fetch → Decode → Execute → repeat
  • CPU can perform billions of cycles per second
Fetch Stage – Key Steps
  1. PC\text{PC} value (address of next instruction) ➔ MAR\text{MAR}
  2. Address sent via Address Bus\text{Address Bus} to RAM
  3. Instruction at that address returned via Data Bus\text{Data Bus} to MDR\text{MDR}
  4. Instruction copied MDR→CIR\text{MDR} \rightarrow \text{CIR}
  5. PC\text{PC} incremented by 11 (points to following instruction)
  6. Instruction passed to Control Unit for decoding
Registers Used in Fetch
  • PC\text{PC} – holds address of next instruction
  • MAR\text{MAR} – holds address being accessed
  • MDR\text{MDR} – temporarily holds data/​instruction fetched
  • CIR\text{CIR} – holds current instruction ready for decode/execute
Decode Stage
  • Control Unit interprets opcode in CIR\text{CIR}
  • Determines required operation, operands, and hardware resources
Execute Stage
  • ALU/Accumulator perform calculation, logic or data movement
  • Results stored in ACC\text{ACC}, registers, or RAM as directed
  • Cycle repeats (return to Fetch)
CPU ↔ RAM Interaction
  • RAM stores currently-needed data & program instructions
  • CPU fetches instructions/data from RAM, processes them, writes back results if needed
  • RAM organised as memory addresses containing either data or instructions
Quick-Recall Exam Points
  • FDE cycle = Fetch→Decode→Execute\text{Fetch} \rightarrow \text{Decode} \rightarrow \text{Execute}
  • Two events in cycle: instruction fetched from memory; instruction decoded/executed; PC incremented, etc.
  • Four main registers in Fetch: PC,MAR,MDR,CIR\text{PC}, \text{MAR}, \text{MDR}, \text{CIR}
  • Buses: Address, Data, Control
  • After Fetch, PC\text{PC} is incremented; this occurs at end of Fetch stage