MOSFET Notes

MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor)

  • Also known as Metal-Insulator Semiconductor FET.
  • Widely used in electronic devices, especially digital circuits, due to their small size, allowing thousands to be fabricated on a single IC.
  • The gate terminal is insulated from the channel.
  • Also referred to as Insulated Gate FET (IGFET).
  • Typically made using silicon (semiconductor), SiO2SiO_2 (insulator), and metal or heavily doped polysilicon (gate electrode).

JFET vs. MOSFET

  • A primary drawback of JFETs is that the gate must be reverse-biased for proper operation, which means:
    • Negative gate operation for n-channel JFETs.
    • Positive gate operation for p-channel JFETs.
  • This limits operation to decreasing channel width (decreasing conductivity) from its zero-bias size, known as depletion-mode operation.
  • MOSFETs have advantages over JFETs, including:
    • High input impedance.
    • Low cost of production.

Types of MOSFETs

  • Two basic types:
    • Depletion-type MOSFET (D-MOSFET): Operates in both depletion and enhancement modes.
    • Enhancement-type MOSFET (E-MOSFET): Operates only in enhancement mode.
  • The construction determines whether a MOSFET is D-MOSFET or E-MOSFET.

D-MOSFET Construction

  • n-channel D-MOSFET construction:
    • A piece of n-type material with a p-type region (substrate) on one side and an insulated gate on the other.
    • Free electrons flow from source to drain through the narrow channel between the gate and substrate.
    • A thin layer of metal oxide (usually silicon dioxide, SiO2SiO_2) is deposited over a portion of the channel.
    • A metallic gate is deposited over the oxide layer, insulated from the channel, forming a capacitor.
      • One plate is the gate, the other is the channel, with SiO2SiO_2 as the dielectric.
    • The substrate is usually connected to the source (S) internally, resulting in three terminals: source (S), gate (G), and drain (D).
    • Either negative or positive voltage can be applied to the gate due to its insulation from the channel.

D-MOSFET Symbols

  • Two types of D-MOSFETs:
    • n-channel D-MOSFET.
    • p-channel D-MOSFET.
  • The p-type substrate constricts the channel between the source and drain.

Circuit Operation of D-MOSFET

  • The gate forms a capacitor.
    • One plate: gate.
    • Other plate: channel with metal oxide layer as the dielectric.
  • Changing gate voltage alters the electric field of the capacitor, changing the resistance of the n-channel.
  • Either negative or positive voltage can be applied to the gate because the gate is insulated.

Depletion Mode

  • Negative gate operation.
  • Electrons on the gate repel free electrons in the n-channel, creating a layer of positive ions.
  • The n-channel is depleted of free electrons, reducing current conduction.
  • Increasing the negative gate voltage decreases the current from source to drain, effectively increasing channel resistance.

Enhancement Mode

  • Positive gate operation.
  • Positive gate induces negative charges (free electrons) in the n-channel.
  • Free electrons are added to those already in the channel, increasing conductivity.
  • Increasing the positive gate voltage increases conduction from source to drain.

Key Points of D-MOSFET Operation

  • Source-to-drain current is controlled by the electric field of the capacitor formed at the gate.
  • The gate of a JFET behaves as a reverse-biased diode, while the gate of a D-MOSFET acts as a capacitor.
  • D-MOSFETs can be operated with positive or negative gate voltage.
  • Negligible gate current flows due to the capacitor formation, resulting in very high input impedance (10,000 MΩΩ to 10,000,00 MΩΩ).
  • Extremely small dimensions of the oxide layer under the gate result in very low input capacitance, making D-MOSFETs useful in high-frequency applications.

D-MOSFET Transfer Characteristic

  • The transfer characteristic curve (transconductance curve) explains the device's behavior.
    • When V<em>GS=0V<em>{GS} = 0, I</em>D=I<em>DSSI</em>D = I<em>{DSS}. This is expected since I</em>DSSI</em>{DSS} is the drain current when the gate and source are shorted (VGS=0V_{GS} = 0).
    • As V<em>GSV<em>{GS} goes negative, I</em>DI</em>D decreases below I<em>DSSI<em>{DSS} until I</em>DI</em>D reaches zero when V<em>GS=V</em>GS(off)V<em>{GS} = V</em>{GS(off)}, similar to JFETs.
    • When V<em>GSV<em>{GS} is positive, I</em>DI</em>D increases above IDSSI_{DSS}.