Definitions

Definitions and Concepts for OCR Computer Science A-level Component 1.1

1.1.1 Structure and Function of the Processor

• Accumulator (ACC):

  • A special register to temporarily store the results of operations performed by the Arithmetic Logic Unit (ALU).

• Address Bus:

  • Carries the memory location address of the register the data is being carried to or from.

• Arithmetic and Logic Unit (ALU):

  • A part of the CPU that performs arithmetic calculations and logical operations on data for the computer programs.

• Buses:

  • A physical set of parallel wires connecting and carrying groups of bits between several components of a computer.

• Cache:

  • A small and fast but expensive memory in the CPU used to store instructions and data that are accessed regularly.

• Clock Speed:

  • The frequency at which the internal clock generates signals switching between 0 and 1.
  • It controls how often instructions are executed and data is fetched.

• Contemporary Processor Architecture:

  • A modern computer architecture combining elements of both Von Neumann and Harvard architectures.

• Control Bus:

  • A bi-directional bus carrying control signals from the Control Unit (CU) to synchronize access and use of data.

• Control Unit (CU):

  • A part of the CPU that controls and manages the execution of instructions.
  • It sends control signals to coordinate execution and controls Fetch-Decode-Execute cycles and buses.

• Current Instruction Register (CIR):

  • A special register that stores the current instruction being executed and decoded.
  • The instructions are divided into operand and opcode.

• Data Bus:

  • A bi-directional bus for carrying data and instructions between the processor and memory.

1.1.2 Fetch-Decode-Execute Cycles

• Fetch-Decode-Execute Cycles:
  • The process of:
  • Fetching: Retrieving instruction from memory by supplying the address.
  • Decoding: Interpreting the instruction and retrieving required data from their addresses.
  • Executing: The CPU carries out the required actions.

1.1.3 Architectures

• Harvard Architecture:

  • A computer architecture that stores data and instructions in separate memories to allow for simultaneous reads.

• Memory Address Register (MAR):

  • A special register that stores the memory address of the next instruction to load or data to use.

• Memory Data Register (MDR):

  • A special register that temporarily stores data to be read from or written to the computer’s memory.

• Number of Cores:

  • A core is a processing unit that handles instructions with its own fetch-execute-decode cycles.
  • Multi-core processors have multiple cores that can run simultaneously.

• Pipelining:

  • A technique where the CPU decodes several instructions simultaneously by:
  • Decoding the next instruction.
  • Fetching the instruction after that while the current one is being decoded.

• Program Counter (PC):

  • A special purpose register that stores the address of the next instruction to execute.

• Registers:

  • Special memory cells that can be accessed quickly, temporarily storing data and control information.

• Von Neumann Architecture:

  • A computer architecture where a single control unit manages program control via a linear sequence of fetch-execute-decode cycles.

1.1.4 Types of Processor

• Complex Instruction Set Computer (CISC):
  • A more complicated and expensive processor design that can execute a series of tasks in a single complex instruction built into the hardware.
  • A variety of instructions leads to less RAM usage, but pipelining is not possible.