Computer Basics and Hardware Notes

Fundamentals of Computer Organization and Architecture

  • Computer Definition:

    • A computer is an electronic device capable of performing calculations, processing data, and making logical decisions.
    • Operates under the control of structured sets of instructions termed computer programs.

  • Core System Division:

    • Hardware: Physical components that interpret and execute programs, store data and programs, and facilitate data transfer to and from external environments.
    • Software: Sets of coded instructions that direct the physical hardware on what tasks to execute and how to perform them.
    • Hardware is non-functional without software; software is operational only when executed on hardware.

  • Five Classic Hardware Components:

    • Processor (CPU): Interprets and executes instructions.
    • Memory: Stores both active programs and raw/processed data.
    • Input Mechanism: Transfers data into the system from the outside world (e.g., keyboard, mouse).
    • Output Mechanism: Displays or transmits processed data to the outside world (e.g., screen, printer).
    • Storage/Transfer Devices: Manages persistent storage and data media (e.g., hard disks, CD-ROMs).

Five Classic Components of a Computer System

  • Six Logical Units of Computer Systems:
    • Input Unit: Receives raw information from input peripherals (keyboard, mouse).
    • Output Unit: Conveys processed information to external devices (display screens, printers).
    • Memory Unit: Provides rapid-access, low-capacity storage for input information and active program data.
    • Arithmetic and Logic Unit (ALU): Performs mathematical operations and evaluates logical decisions.
    • Central Processing Unit (CPU): Supervises, regulates, and coordinates the overall operations of all other system sections.
    • Secondary Storage Unit: Provides non-volatile, high-capacity, low-cost long-term storage for inactive programs and persistent data.

System Unit Components and Motherboard Architecture

  • System Unit Housing:
    • Enclosed case constructed from metal or plastic designed to safeguard internal electronic components against physical damage.
    • Universal component present in all computers, manufactured in a wide range of shapes and sizes.

Desktop Computer System Unit Tower

  • Primary Components within the System Unit:
    • Processor (CPU): Interprets and executes basic computing instructions.
    • Memory Modules: Temporarily holds data awaiting processing and instructions queued for execution.
    • Motherboard (System Board): Main circuit board interconnecting processor chips, memory modules, and expansion cards.
    • Adapter Cards (Expansion Slots): Circuit boards inserted into expansion slots to supply specialized functionality not built directly into the motherboard.
    • Ports: Connection sockets for attaching external peripheral devices to the internal system.
    • Drive Bays: Internal mounting structures that accommodate disk drives.
    • Power Supply: Converts electrical power to supply internal components with operational current.
    • Heat Sink: Thermal management structure mounted over high-temperature chips to dissipate thermal energy.

Detailed Motherboard Component Breakdown

Data Representation and Coding Schemes

  • Binary Data Principles:

    • Computers process data using a base-2 binary system consisting of two discrete digits: 00 (representing off) and 11 (representing on).
    • Bit: The smallest individual unit of data a computer can manipulate.
    • Byte: A grouped set of 88 bits capable of representing alphanumeric characters, digits, or symbols.

  • Standardized Coding Schemes:

    • Coding schemas define specific binary bit combinations used to translate numeric values into characters.
    • ASCII (American Standard Code for Information Interchange): Standard 8-bit coding format.
    • EBCDIC (Extended Binary Coded Decimal Interchange Code): IBM-developed 8-bit character encoding system.

ASCII vs EBCDIC Character Encoding Table

  • Binary Encoding Equivalence Reference:
    • Symbol '0': ASCII 00110000 | EBCDIC 11110000
    • Symbol '1': ASCII 00110001 | EBCDIC 11110001
    • Symbol '2': ASCII 00110010 | EBCDIC 11110010
    • Symbol '3': ASCII 00110011 | EBCDIC 11110011
    • Symbol '4': ASCII 00110100 | EBCDIC 11110100
    • Symbol '5': ASCII 00110101 | EBCDIC 11110101
    • Symbol '6': ASCII 00110110 | EBCDIC 11110110
    • Symbol '7': ASCII 00110111 | EBCDIC 11110111
    • Symbol '8': ASCII 00111000 | EBCDIC 11111000
    • Symbol '9': ASCII 00111001 | EBCDIC 11111001
    • Symbol 'A': ASCII 01000001 | EBCDIC 11000001
    • Symbol 'B': ASCII 01000010 | EBCDIC 11000010
    • Symbol 'C': ASCII 01000011 | EBCDIC 11000011
    • Symbol 'D': ASCII 01000100 | EBCDIC 11000100
    • Symbol 'E': ASCII 01000101 | EBCDIC 11000101

CPU Internal Structure and Machine Cycles

  • Data Processing Loop:
    • System operation involves continuously moving data from input/storage into CPU memory, processing it via the Control Unit and ALU, and directing outputs to storage or display devices.

CPU Data Flow and System Component Interconnection

  • Four-Step Machine Cycle:
    1. Fetch: The Control Unit retrieves program instructions from main memory.
    2. Decode: The Control Unit interprets the fetched instruction into operational signals.
    3. Execute: The Arithmetic/Logic Unit executes the decoded mathematical or logical command.
    4. Store: Results generated during execution are written back into main memory registers.

The Four-Step Machine Execution Cycle

  • CPU Primary Sub-units:

    • Datapath: Consists of the ALU and temporary internal storage units (registers) interconnected by an internal data bus linked directly to main memory.
    • Control Unit: Oversees operational sequencing, instruction flow, and precise timing of data transfers across CPU components.

  • Arithmetic/Logic Unit (ALU) Operations:

    • Arithmetic Operations: Standard arithmetic tasks including addition, subtraction, multiplication, and division.
    • Logical Comparisons:
    • Equal-to condition: Evaluates if two values are identical.
    • Less-than condition: Evaluates if a target value is smaller than a baseline value.
    • Greater-than condition: Evaluates if a target value exceeds a baseline value.

Register Organization within the CPU

  • Register Characteristics:

    • Internal, high-speed temporary storage cells situated directly within the CPU structure.
    • Function outside standard system memory to deliver maximum data access speeds under direct control of the Control Unit.

  • General Purpose Registers:

    • User-visible registers accessible by assembly/machine instructions to store intermediate operation results.
    • Examples in Intel Microprocessors include four standard registers: AX, BX, CX, and DX.

  • Special Purpose Registers:

    • User-invisible hardware registers managed automatically by internal CPU logic:
    • PC (Program Counter): Stores the memory address of the next sequential instruction queued for execution.
    • MAR (Memory Address Register): Holds the active memory address currently being read from or written to via the Address Bus.
    • MDR / MBR (Memory Data Register / Memory Buffer Register): Serves as the operational gate between external memory buses and internal CPU components. All incoming or outgoing data must pass through the MDR.
    • IR (Instruction Register): Stores the binary representation of the instruction currently being executed after retrieval from memory.

CPU Internal Micro-architecture, Registers, and Internal Buses

System Communication: Buses, Clocks, and Interrupts

  • Bus Interconnects:
    • A bus consists of parallel electrical conductor lines carrying individual data bits simultaneously across system modules.

System Bus Interconnections between CPU, Memory, and I/O

  • Primary Bus Types:

    • Processor-Memory Bus: Short, ultra-high-speed dedicated bus optimized to match memory timing and maximize throughput bandwidth.
    • I/O Bus: Extended-length bus designed to accommodate diverse peripheral devices operating across varied bandwidth speeds.
    • Backplane Bus: System-wide structural bus integrating CPU, main memory modules, and peripheral interface slots onto a unified interface.

  • System Clock Mechanics:

    • Master clock circuit generating precise pulses to synchronize internal operations across system components.
    • Every operation requires a fixed number of clock cycles to complete.
    • Clock frequency is expressed in Megahertz (MHz\text{MHz}) or Gigahertz (GHz\text{GHz}).
    • Clock Cycle Duration Equation: Clock Cycle Time=1Clock Frequency\text{Clock Cycle Time} = \frac{1}{\text{Clock Frequency}}
    • Example: A system operating with an 800 MHz800\,\text{MHz} clock frequency has a calculated cycle time of: Cycle Time=1800×106 Hz=1.25 ns\text{Cycle Time} = \frac{1}{800 \times 10^6\,\text{Hz}} = 1.25\,\text{ns}
    • Raw clock speed must not be evaluated as the sole indicator of overall CPU system performance.

  • Interrupt Handling:

    • Hardware mechanism causing the processor to suspend normal program execution to address higher-priority external or internal events.
    • Nonmaskable Interrupts: Urgent hardware events that cannot be delayed or ignored by CPU control logic.
    • Maskable Interrupts: Standard priority interrupts that can be temporarily disabled or postponed via software registers.
    • Primary Triggers for Interrupt Signals:
    • Peripheral I/O service requests.
    • Arithmetic errors (e.g., division by zero).
    • Arithmetic underflow or overflow conditions.
    • Critical hardware malfunctions.
    • Software execution breakpoints set during program debugging.
    • Invalid instruction execution codes stemming from memory pointer faults.

Memory Organization, Capacity, and Addressing

  • Memory Architecture Principles:
    • Linear array of addressable storage cells structured as bit matrices where each row length corresponds to machine word size.
    • Memory locations possess unique sequential numerical addresses starting at index zero (00).

Comparison of 8-bit vs 16-bit Memory Address Structures

  • Addressing and Chip Specifications:

    • Systems are designed as byte-addressable or word-addressable (e.g., half-word addressable at 16 bits).
    • Memory chip configurations are specified as Length×Width\text{Length} \times \text{Width}.
    • Example: A 4M×164\text{M} \times 16 RAM chip architecture provides 4 gigabytes4\,\text{gigabytes} of addressable 16-bit storage locations.

  • Standardized Capacity Scale Values:

    • Kilobyte (KB / K): Approximate count = 1,0001,000 bytes (10310^3) | Exact count = 1,0241,024 bytes (2102^{10}).
    • Megabyte (MB): Approximate count = 1,000,0001,000,000 bytes (10610^6) | Exact count = 1,048,5761,048,576 bytes (2202^{20}).
    • Gigabyte (GB): Approximate count = 1,000,000,0001,000,000,000 bytes (10910^9) | Exact count = 1,073,741,8241,073,741,824 bytes (2302^{30}).
    • Terabyte (TB): Approximate count = 1,000,000,000,0001,000,000,000,000 bytes (101210^{12}) | Exact count = 1,099,511,627,7761,099,511,627,776 bytes (2402^{40}).

Memory Technologies: RAM vs. ROM Systems

  • Random Access Memory (RAM):

    • Function: Serves as main system memory to store active code and real-time execution data.
    • Volatility: Highly volatile; completely loses all stored data when electrical power is disconnected.
    • DRAM (Dynamic RAM):
    • Made of micro-capacitors that continuously lose electrical charge over time.
    • Requires periodic refresh cycles every few milliseconds to prevent data loss.
    • Lower manufacturing cost, high component density (storing many bits per chip), low power draw, low thermal generation.
    • Variations include: Multibank DRAM (MDRAM), Fast-Page Mode (FPM) DRAM, Extended Data Out (EDO) DRAM, Burst EDO DRAM (BEDO DRAM), Synchronous Dynamic RAM (SDRAM), Synchronous-Link (SL) DRAM, Double Data Rate (DDR) SDRAM, Direct Rambus (DR) DRAM.
    • SRAM (Static RAM):
    • Transistor-based logic circuit that retains data without requiring refresh cycles.
    • Exceptionally fast operational speed, but significantly more expensive, less dense, and generates higher thermal output.
    • Primary application: Used to construct high-speed processor Cache memory.
    • Variations include: Asynchronous SRAM, Synchronous SRAM, and Pipeline Burst SRAM.

  • Read-Only Memory (ROM):

    • Function: Stores non-volatile permanent or semi-permanent system instructions (e.g., BIOS, startup routines) that persist across power cycles.
    • Applications: Toys, automobile engine control modules, calculators, laser printers.
    • ROM Variants:
    • Standard ROM: Factory hardwired during manufacturing; unalterable.
    • PROM (Programmable ROM): Field-programmable once by users using specialized programmer equipment; permanently locked post-programming.
    • EPROM (Erasable PROM): Reprogrammable semiconductor memory. Requires high-intensity ultraviolet (UV) light exposure to completely clear contents before rewrite.
    • EEPROM (Electrically Erasable PROM): Electronically erasable memory using targeted electric fields without special tools. Allows selective byte-by-byte erasure and editing.
    • Flash Memory: Advanced form of EEPROM supporting block-level reading, writing, and erasing, overcoming single-byte editing bottlenecks.

Memory Hierarchy Pyramid and Cache Systems

  • Memory Hierarchy Concept:
    • System design trade-off balancing operational speed, storage capacity, and financial cost.
    • High-speed memory costs significantly more per bit and is placed closest to the CPU in smaller capacities; lower-speed storage is positioned further away in massive capacities.

The Computer Memory Hierarchy Pyramid

  • Hierarchical Storage Tiers:

    • Registers:
    • Access Latency: 1 ns→2 ns1\,\text{ns} \rightarrow 2\,\text{ns}
    • Domain: System Level | Relative Cost: Highest
    • Level 1 (L1) Cache:
    • Access Latency: 3 ns→10 ns3\,\text{ns} \rightarrow 10\,\text{ns}
    • Domain: System Level | Capacity: Typical size 8 KB8\,\text{KB} to 16 KB16\,\text{KB}; built directly on the CPU silicon chip.
    • Level 2 (L2) Cache:
    • Access Latency: 25 ns→50 ns25\,\text{ns} \rightarrow 50\,\text{ns}
    • Domain: System Level | Capacity: Typical size 256 KB256\,\text{KB} to 512 KB512\,\text{KB}; positioned between the CPU core and Main Memory.
    • Main Memory (RAM):
    • Access Latency: 30 ns→90 ns30\,\text{ns} \rightarrow 90\,\text{ns}
    • Domain: Online Level
    • Fixed Rigid Disk (Hard Drive):
    • Access Latency: 5 ms→20 ms5\,\text{ms} \rightarrow 20\,\text{ms}
    • Domain: Online / Near Line Level
    • Optical Disk (Jukeboxes):
    • Access Latency: 100 ms→5 s100\,\text{ms} \rightarrow 5\,\text{s} (when volume is mounted)
    • Domain: Near Line / Offline Level
    • Magnetic Tape (Robotic Libraries):
    • Access Latency: 10 s→3 min10\,\text{s} \rightarrow 3\,\text{min} (when volume is mounted)
    • Domain: Offline Level | Relative Cost: Lowest

  • Cache Memory Operational Principles:

    • Cache functions as Content Addressable Memory (CAM), searched directly by binary data content rather than memory address indexes.
    • Stores copies of recently accessed data blocks to eliminate main memory access delays.
    • Search latency increases with cache volume; hence, multi-tier split caches (L1 vs L2) are used to maintain high hit rates.
    • Data Request Pipeline: CPU queries L1 Cache →\rightarrow queries L2 Cache →\rightarrow queries Main Memory →\rightarrow queries Secondary Rigid Disk. When data is found, it is copied into cache alongside adjacent memory elements.

Peripheral Input/Output Devices and Secondary Storage

  • Input/Output (I/O) Architecture:

    • Peripherals allow human-machine interaction and data movement between internal memory and external hardware.
    • Input Devices: Keyboards, computer mice, card readers, image scanners, voice recognition hardware, touch screens.
    • Output Devices: Display screens/monitors, paper printers, plotters, audio speakers.

  • Device Interface Components:

    • Peripherals do not connect directly to internal CPU buses; specialized controller interfaces bridge signal conversions.
    • Example: Graphics Processing Units (GPUs) translate system bus streams into output formats for displays.

  • I/O Register Communication Methods:

    • Memory-Mapped I/O: Peripheral device control registers are assigned addresses within the standard main memory map. The CPU executes I/O tasks using regular memory instructions.
    • Instruction-Based I/O: The CPU uses dedicated hardware control lines and specialized machine instructions reserved specifically for peripheral read/write operations.

  • Secondary Storage Systems:

    • Physical media providing non-volatile retention of data, applications, and operating system software for future reuse.
    • Storage media formats: Internal hard disks, floppy diskettes, Zip disks, optical CDs/DVDs, magnetic tapes, PC Cards, flash memory storage cards, USB flash drives, microfilm units.