Sequential Logic Circuits: Flip-Flops, Registers, Counters, and Finite State Machines

Combinational vs. Sequential Circuits: Principles and Structural Models

Digital logic circuits are divided into two fundamental classifications: combinational circuits and sequential circuits. Their operational distinction lies in the presence or absence of memory elements and internal feedback.

A combinational circuit produces outputs that are solely a function of its current inputs at any given instant. It possesses no memory of past inputs or historical events. For any specified set of input variables, there is an immediate and unique output pattern, subject only to the physical propagation delays of the internal logic gates. Representative examples of combinational circuits include logic gates, adders, subtractors, multiplexers, demultiplexers, encoders, and decoders.

A sequential circuit produces outputs that depend not only on the present input values but also on the present state of the circuit. The present state is a stored representation of the history of past inputs, retained within internal memory elements. Consequently, applying an identical set of inputs to a sequential circuit at different times can yield entirely different outputs depending on the stored state.

As shown in the block diagram, a sequential circuit consists of combinational logic coupled with a memory section constructed from flip-flops or latches. The combinational logic receives external inputs as well as present-state signals fed back from the flip-flops. It generates the circuit's external outputs and computes the next-state signals required to update the memory elements. A periodic clock signal ($CLK$) synchronizes the updating of these memory elements across the system.

Sequential circuits serve as the foundation of digital computation, enabling counting, timing generation, temporary and bulk data storage, and the execution of finite-state decision logic.

The Set-Reset (SR) Latch and Flip-Flop

Memory cells that store a single binary bit ($1$ or $0$) are categorized into latches and flip-flops. A latch is a level-sensitive device whose output changes immediately in response to input changes while enabled. A flip-flop is a synchronous, clock-controlled device whose state transitions occur exclusively at specific transitions (rising or falling edges) or active phases of a clock signal.

SR Latch Using Cross-Coupled NOR Gates

The fundamental 1-bit memory cell can be constructed using two cross-coupled NOR gates, designated as NOR 1 and NOR 2. The output of NOR 1 represents the true state ($Q$), which is fed back into one of the inputs of NOR 2. The output of NOR 2 represents the complementary state ($Q'$), which is fed back into one of the inputs of NOR 1.

The external inputs are Set ($S$) and Reset ($R$). The circuit exhibits active-high operation:

When $S = 0$ and $R = 0$, the cross-coupling latches the present state, and the outputs remain fixed. Setting $S = 1$ and $R = 0$ forces the output $Q$ to $1$ (Set). Setting $S = 0$ and $R = 1$ forces $Q$ to $0$ (Reset). If both inputs are simultaneously asserted ($S = 1, R = 1$), both NOR outputs are forced to logic $0$, violating the complementary relationship $Q \neq Q'$. Furthermore, if both inputs transition simultaneously from $1$ to $0$, the final state becomes indeterminate and unpredictable due to unequal propagation delays through the two gates.

SR Latch Using Cross-Coupled NAND Gates

An alternative implementation utilizes two cross-coupled NAND gates. In this configuration, the control inputs are active-low, commonly denoted as $S'$ (or $\overline{S}$) and $R'$ (or $\overline{R}$).

The behavior of the cross-coupled NAND latch is summarized below:

Because the inputs are active-low, asserting $S' = 0$ (with $R' = 1$) sets the latch to $Q = 1$. Asserting $R' = 0$ (with $S' = 1$) resets the latch to $Q = 0$. When $S' = 1$ and $R' = 1$, the latch retains its previous state. The forbidden condition occurs when $S' = R' = 0$, which forces both $Q$ and $Q'$ to logic $1$.

Clocked SR Flip-Flop

To synchronize state updates with a system clock, steering logic is added to the basic latch. In the clocked SR flip-flop, two AND gates precede an internal NOR-based SR latch, with one input of each AND gate tied to a common clock line ($CLK$).

When $CLK = 0$, both AND gates output logic $0$, isolating the inputs $S$ and $R$ from the latch and maintaining the hold condition ($Q(\text{next}) = Q$). When $CLK = 1$, the AND gates permit the values of $S$ and $R$ to pass into the latch.

Characteristic Equation, Characteristic Table, and Excitation Table

The algebraic relationship describing the next-state behavior of an SR flip-flop is given by its characteristic equation:

$Q(\text{next}) = S + R' \cdot Q$

This equation is valid strictly under the operational constraint:

$S \cdot R = 0$

The characteristic table lists the next state ($Q_{n+1}$) for every combination of inputs $S$, $R$, and present state ($Q_n$):

The excitation table specifies the required input combination ($S$ and $R$) to achieve a desired transition from a known present state ($Q_n$) to a designated next state ($Q_{n+1}$):

Here, $X$ denotes a don't-care condition. For example, to maintain a present state of $0$ ($Q_n = 0 \rightarrow Q_{n+1} = 0$), $S$ must be $0$, while $R$ can be either $0$ (hold) or $1$ (reset).

Worked Example: State Progression

Consider an SR flip-flop initially at state $Q_n = 0$.

1. A clock pulse is applied with inputs $S = 1$ and $R = 0$:

$Q(\text{next}) = S + R' \cdot Q = 1 + (1 \cdot 0) = 1 + 0 = 1$

The flip-flop sets to $Q = 1$.

2. On the subsequent clock pulse, the inputs change to $S = 0$ and $R = 1$:

$Q(\text{next}) = S + R' \cdot Q = 0 + (0 \cdot 1) = 0 + 0 = 0$

The flip-flop resets back to $Q = 0$.

Practical Applications and System Limitations

The SR flip-flop is utilized in specific digital sub-circuits:

• Switch Debouncing: Interfacing mechanical switches or pushbuttons produces transient voltage spikes due to contact bounce. An SR latch eliminates these erratic oscillations, yielding clean, single-transition digital pulses.

• Control Flags: It serves as a simple latching flag to capture asynchronous status events, remaining set until explicitly cleared by control logic.

• Basic Storage Registers: It functions as an elemental 1-bit memory cell.

• Foundational Building Block: It constitutes the internal core around which more sophisticated flip-flops are constructed.

The primary limitation of the SR flip-flop is the invalid output state produced when $S = R = 1$. Circuit designers must introduce external gating or select alternative flip-flop architectures to prevent this condition.

The Universal JK Flip-Flop, Race-Around Condition, and Master-Slave Architecture

The JK flip-flop eliminates the undefined state of the SR flip-flop while retaining its Set, Reset, and Hold functions. It is designated as a universal flip-flop because suitable external connections enable it to emulate SR, D, or T flip-flops.

Logic Implementation and Functional Behavior

The JK flip-flop is constructed by adding feedback from the outputs of an SR latch to its input gating logic. Specifically, the complementary output $Q'$ is routed back into the AND gate associated with input $J$, and the true output $Q$ is routed back into the AND gate associated with input $K$.

This cross-coupled feedback ensures that when $J = 1$ and $K = 1$, only the gate opposite the current state is enabled. Consequently, instead of entering a forbidden state, the flip-flop toggles, inverting its output on every active clock pulse.

Characteristic and Excitation Analysis

The algebraic characteristic equation of the JK flip-flop is derived using Karnaugh mapping:

$Q(\text{next}) = J \cdot Q' + K' \cdot Q$

The characteristic table defines the full next-state mapping across all input combinations:

The excitation table defines the inputs $J$ and $K$ required to induce a specified state transition:

The Race-Around Condition

In a level-triggered JK flip-flop, a timing pathology known as the race-around condition occurs when $J = 1$, $K = 1$, and the clock pulse duration ($t_w$) exceeds the internal gate propagation delay ($t_p$) of the flip-flop.

Under these conditions, if the flip-flop starts at $Q = 0$, asserting $J = K = 1$ causes the output to switch to $Q = 1$ after delay $t_p$. However, because the clock remains high ($CLK = 1$), this new output $Q = 1$ feeds back into the $K$ gate, causing the circuit to toggle again to $Q = 0$ after another interval $t_p$. The output continues oscillating between $0$ and $1$ at intervals of $t_p$ for the entire duration that $CLK = 1$:

$Q(t_0) = 0 \longrightarrow Q(t_0 + t_p) = 1 \longrightarrow Q(t_0 + 2t_p) = 0 \longrightarrow Q(t_0 + 3t_p) = 1 \longrightarrow Q(t_0 + 4t_p) = 0 \dots$

When the clock signal falls back to $0$, the final state of $Q$ is indeterminate, depending entirely on the exact ratio of the pulse width to the internal propagation delay.

To prevent the race-around condition:

1. The clock pulse width must be strictly smaller than the propagation delay ($t_w < t_p$), which is difficult to guarantee across manufacturing and temperature variations.

2. Edge-triggered flip-flops can be employed, sampling inputs only during the narrow transition threshold of the clock.

3. A Master-Slave JK architecture can be implemented.

Master-Slave JK Flip-Flop Architecture

A Master-Slave JK flip-flop connects two separate flip-flops in series with complementary clocking:

1. Master Flip-Flop: A positive-level-triggered JK stage receiving external inputs $J$ and $K$, clocked directly by $CLK$.

2. Slave Flip-Flop: A negative-level-triggered (or inverted) JK stage whose inputs are driven by the outputs ($Q_m, Q_m'$) of the master, clocked by $CLK'$ (via an inverter).

During circuit operation:

• While $CLK = 1$, the master is active and responds to inputs $J$ and $K$, updating intermediate nodes $Q_m$ and $Q_m'$. Concurrently, $CLK' = 0$, keeping the slave disabled and isolated, which holds the primary outputs $Q$ and $Q'$ stable.

• While $CLK = 0$, the master is disabled and isolated from any further input fluctuations. Concurrently, $CLK' = 1$, enabling the slave to copy the states $Q_m$ and $Q_m'$ to the external outputs $Q$ and $Q'$.

Because the master and slave are never active simultaneously, the complete circuit responds to inputs during the clock high period but updates its external outputs only when the clock transitions low. This two-phase transfer prevents continuous feedback oscillations and eliminates the race-around condition.

Step-by-Step State Execution Trace

Consider a JK flip-flop starting from an initial state $Q = 0$ subjected to four successive clock pulses:

For Clock Pulse 2 ($J = 1, K = 1, Q = 1$), applying the characteristic equation yields:

$Q(\text{next}) = J \cdot Q' + K' \cdot Q = (1 \cdot 0) + (0 \cdot 1) = 0 + 0 = 0$

The state flips from $1$ to $0$. After four clock pulses, the final state is $Q = 1$.

Data (D) and Toggle (T) Flip-Flops

The D and T flip-flops are single-input variations derived by simplifying the SR and JK architectures to serve specific functional roles in digital systems.

D Flip-Flop (Data / Delay Flip-Flop)

The D flip-flop captures and stores the logic level present on its single data input line ($D$). It is constructed by taking a clocked SR flip-flop and placing an inverter between the Set and Reset terminals, enforcing $S = D$ and $R = D'$.

Because the inputs to the internal SR stage are always complementary, the condition $S = R = 1$ is structurally impossible, eliminating the invalid state by design.

The characteristic equation is:

$Q(\text{next}) = D$

The characteristic table and excitation table are structured as follows:

The excitation requirement for a D flip-flop is straightforward: the input $D$ must match the desired next state $Q_{n+1}$, independent of the present state $Q_n$. Due to its reliable data capture, the D flip-flop is the primary element used in registers, memory arrays, shift registers, and bus synchronizers.

T Flip-Flop (Toggle Flip-Flop)

The T flip-flop has a single input ($T$). It is constructed by tying together the $J$ and $K$ inputs of a JK flip-flop ($J = K = T$).

Tying the inputs together eliminates the independent Set and Reset states, leaving only Hold and Toggle:

The characteristic equation is expressed using the exclusive-OR ($\oplus$) operation:

$Q(\text{next}) = T \oplus Q = T \cdot Q' + T' \cdot Q$

The characteristic and excitation tables are:

The excitation table is symmetric: $T = 0$ whenever the state is to be preserved ($Q_n = Q_{n+1}$), and $T = 1$ whenever the state is to be inverted. This toggle capability makes the T flip-flop standard in binary counters and frequency division circuits.

Comparative Evaluation of Flip-Flop Architectures

Comparative Worked Example: D vs. T Flip-Flop State Traces

Starting from an initial state $Q = 0$, both flip-flops are evaluated across four clock cycles with specific input sequences:

For the D Flip-Flop ($Q_{n+1} = D$):

• Pulse 1: $D = 1 \implies Q = 1$

• Pulse 2: $D = 1 \implies Q = 1$

• Pulse 3: $D = 0 \implies Q = 0$

• Pulse 4: $D = 1 \implies Q = 1$

For the T Flip-Flop ($Q_{n+1} = T \oplus Q$):

• Pulse 1: $T = 1, Q_n = 0 \implies Q_{n+1} = 1 \oplus 0 = 1$

• Pulse 2: $T = 0, Q_n = 1 \implies Q_{n+1} = 0 \oplus 1 = 1$

• Pulse 3: $T = 1, Q_n = 1 \implies Q_{n+1} = 1 \oplus 1 = 0$

• Pulse 4: $T = 1, Q_n = 0 \implies Q_{n+1} = 1 \oplus 0 = 1$

Both flip-flops finish with a final state of $Q = 1$.

Registers and Data Storage Systems

A register is a group of flip-flops sharing a common clock that stores an $n$-bit binary word as a unified entity. An $n$-bit register uses $n$ flip-flops, typically D flip-flops, and provides basic working storage within central processing units, peripheral controllers, and system buses.

Registers fall into two main classes: buffer (storage) registers, which load and hold words in parallel without lateral movement, and shift registers, which move their bits positionally on clock pulses.

4-Bit Parallel-In Parallel-Out (PIPO) Buffer Register

A basic buffer register stores multi-bit data temporarily so it can be sampled or routed asynchronously later. A 4-bit buffer register uses four D flip-flops (FF0 to FF3) sharing a single clock line.

External data lines ($D_0, D_1, D_2, D_3$) connect directly to the respective flip-flop inputs. When an active rising clock edge occurs, each input bit $D_i$ transfers simultaneously into its corresponding flip-flop stage, updating outputs $Q_0, Q_1, Q_2, Q_3$ in parallel during a single clock cycle.

Because all bits transfer in parallel, a buffer register executes no internal bit shifting. It isolates internal bus segments, synchronizes data transfers between subsystems operating at different clock rates, and implements processor register files (such as accumulators and general-purpose registers).

Shift Registers: Operational Topologies, Shifting Sequences, and Counters

A shift register is an array of cascaded flip-flops whose outputs feed directly into the inputs of adjacent stages. When clocked, the entire stored binary word moves incrementally by one bit position to the left or right.

Shift registers are categorized by how data enters and exits the array: Serial-In Serial-Out (SISO), Serial-In Parallel-Out (SIPO), Parallel-In Serial-Out (PISO), and Parallel-In Parallel-Out (PIPO).

Serial-In Serial-Out (SISO) Shift Register

In a 4-bit SISO register, four D flip-flops (FF0, FF1, FF2, FF3) are connected in series. The output $Q$ of each flip-flop drives the data input $D$ of the next stage. A single input line feeds FF0, and output data is taken solely from FF3.

Data enters sequentially, one bit per clock cycle, and propagates through the cascade. Loading an $n$-bit word requires $n$ clock cycles, and reading it out serially requires another $n$ clock cycles. Consequently, a SISO register acts as an $n$-cycle digital delay line.

Shifting Sequence for Word $1011$

Loading the word $1011$ into the register (least significant bit first: $1$, then $1$, then $0$, then $1$) proceeds as follows:

After 4 clock pulses, the complete 4-bit word resides within the register ($Q_0=1, Q_1=0, Q_2=1, Q_3=1$).

Serial-In Parallel-Out (SIPO) Shift Register

A SIPO register receives data serially via a single line but provides parallel access to every flip-flop output ($Q_0, Q_1, Q_2, Q_3$). It converts serial data into parallel words, making it standard in communication receivers (e.g., UART and SPI) to convert bit-serial transmission lines into parallel bus words for processors.

Data shifts into the register over $n$ clock pulses. Once loaded, all $n$ bits are read simultaneously from the parallel outputs in a single clock cycle ($0$ delay cycles for reading).

Parallel-In Serial-Out (PISO) Shift Register

A PISO register accepts a complete parallel data word along lines $B_0, B_1, B_2, B_3$ and outputs it serially over a single line. Multiplexers precede each flip-flop input, controlled by a shared $SHIFT / \overline{LOAD}$ signal.

• When $SHIFT / \overline{LOAD} = 0$ ($\overline{LOAD}$ active), the multiplexers select parallel inputs $B_0 - B_3$. On the next clock edge, the entire word loads into the flip-flops simultaneously (1 clock pulse).

• When $SHIFT / \overline{LOAD} = 1$, the multiplexers switch to select the output of the preceding flip-flop ($Q_{i-1}$). Subsequent clock pulses shift the word rightward by one bit per cycle, emerging serially from FF3.

Worked Trace: PISO Serialization

Consider a PISO register loaded with the parallel word $Q_3 Q_2 Q_1 Q_0 = 1 1 0 1$:

Each pulse shifts the contents rightward ($Q_0 \leftarrow Q_1, Q_1 \leftarrow Q_2, Q_2 \leftarrow Q_3$), filling the most significant bit ($Q_3$) with $0$. After 4 clock cycles, the serial output line has produced the bits $1, 0, 1, 1$, and the register is cleared to $0000$.

Bidirectional and Universal Shift Registers

A bidirectional shift register can shift stored bits either right or left based on a mode control signal. Gating logic at each flip-flop input selects between the left neighbor's output ($Q_{i-1}$) to shift right and the right neighbor's output ($Q_{i+1}$) to shift left. In arithmetic units, shifting left by one bit multiplies an unsigned binary integer by $2$, while shifting right divides it by $2$.

A Universal Shift Register integrates multiple functional modes into a single circuit, typically using 4x1 multiplexers to drive each flip-flop input.

Mode selection is governed by two control lines, $S_1$ and $S_0$:

Standard integrated circuits such as the commercial IC 74194 implement this universal shift register architecture.

Shift Register Counters: Ring Counter and Johnson Counter

Connecting the output of the final stage of a shift register back into the input of the first stage forms a circulating shift register counter.

Ring Counter

A ring counter recirculates the true output of the final flip-flop back into the data input of the initial flip-flop ($Q_{n-1} \rightarrow D_0$).

The register is initialized with a single logic $1$ (e.g., $1000$ for a 4-bit counter). Clock pulses circulate this isolated $1$ around the loop:

An $n$-stage ring counter provides $n$ unique states. Because exactly one flip-flop output is active at any point, the state is self-decoding, eliminating the need for an external decoding network to drive sequential timing lines.

Johnson (Twisted-Ring) Counter

A Johnson counter connects the complemented output of the final stage back to the input of the first stage ($Q'_{n-1} \rightarrow D_0$). Starting from an initialized state of $0000$, inverted bits fill and subsequently clear the register:

An $n$-stage Johnson counter cycles through $2n$ unique states using $n$ flip-flops, doubling the state count of a standard ring counter while requiring simpler decoding logic than binary counters.

Shift Register Performance and Topological Summary

Asynchronous (Ripple) Counters

A counter is a sequential circuit that cycles through a predetermined sequence of states upon the arrival of clock pulses. Counters are classified by their clock distribution into asynchronous (ripple) counters and synchronous counters.

In an asynchronous counter, flip-flops do not share a common clock line. Only the first stage (FF0, Least Significant Bit) receives the external system clock. Each subsequent stage is clocked by the output ($Q$ or $Q'$) of the preceding flip-flop, causing state changes to ripple sequentially down the chain.

2-Bit Asynchronous UP Counter

A 2-bit ripple UP counter uses two T flip-flops with their $T$ inputs tied to logic $1$ ($T_0 = T_1 = 1$), operating in toggle mode.

The external clock drives FF0, causing output $Q_0$ to toggle on each active clock edge. Output $Q_0$ is routed to the clock input of FF1, which triggers on the falling edge ($1 \rightarrow 0$) of $Q_0$. As a result, FF1 toggles at half the frequency of FF0.