EENG3150 Digital Technologies - Lecture 3

Applications of Flip-Flops

• Data registers

• Shift registers

• Divide-by-2 operation

• Parallel-to-serial converter

• Serial-to-parallel converter

• Sequence generators

• Counters

• Binary counters

• BCD (binary coded decimal) counters

Hierarchical Design

• Allows re-use of a circuit.

• Define circuit as a module.

• Re-use of common modules

• D-type Flip-flop: D Q Q Pr Cl

Data Registers

• 1-bit data register

4-bit Data Register

A 4-bit data register consists of four D-type flip-flops, each storing one bit of data. All flip-flops are connected to a common clock signal (CLK). The inputs are labeled IN0, IN1, IN2, and IN3, and the outputs are OUT0, OUT1, OUT2, and OUT3, corresponding to each flip-flop.

Shift Registers

• 4-bit shift register

• Registers are composed of flip-flops (ff1, ff2, ff3, ff4) connected in series.

• Data input (Din) provides the serial input to the register.

• A common clock signal (CLOCK) synchronizes the shift operation.

Example

• Initial conditions: ‘1’ loaded into ff1, ‘1’ loaded into ff2, ‘0’ loaded into ff3, ‘1’ loaded into ff4.

• DIN (data-in) is held at 0.

• Initial conditions can be set by using the asynchronous inputs

• 1 1 0 1 where D1, D2, D3, D4 are connected to Q1, Q2, Q3 and Q4 respectively.

4-bit Shift Register: Logical Shift Right (LSR)

• On the first clock rising edge:

  • the ‘0’ on din is loaded into ff1

  • the ‘1’ in ff1 is transferred to ff2

  • … the ‘1’ in ff4 is lost to the outside

Example

• Initial State: 1 1 0 1, DIN = 0

• After one clock cycle: 0 1 1 0, the rightmost '1' shifts out and is lost.

Numerical Representation of LSR

The lecture provides an example of a 4-bit register undergoing logical shift right (LSR) operations with accompanying binary, decimal representations, and carry bits. Given the initial binary number 1101, which is equivalent to the decimal number 13, the LSR operation proceeds as follows:

1. Initial State: Binary 1101 (Decimal 13)

2. First Clock Cycle: The binary number shifts right, with a '0' entering from the left and the right most bit shifting out 0110 (Decimal 6). The carry bit becomes '1' because the rightmost '1' was shifted out.

3. Second Clock Cycle: The binary number shifts right again 0011 (Decimal 3), carry is 0.

4. Third Clock Cycle: The binary number shifts right again 0001 (Decimal 1), carry is 1.

5. Fourth Clock Cycle: The binary number shifts right again 0000 (Decimal 0), carry is 1.

• Each shift operation effectively divides the number by 2 (integer division).

• The carry bit indicates whether the shifted-out bit was a 1 or a 0.

Divide-by-2 Operation

• On the first clock rising edge:

  • the ‘0’ on din is loaded into ff1

  • the ‘1’ in ff1 is transferred to ff2

  • … the ‘1’ in ff4 becomes the carry bit

• The value in the register is effectively divided by 2 with each clock cycle, and the remainder is output as the carry bit.

Parallel-to-Serial Converter

• Converts parallel data inputs into a serial data output.

• Parallel Data in → Serial Data Out

Operation

1. Load data into flip-flops using Preset and Clear inputs.

2. Clock signal shifts the data out serially.

• Example showing a loaded register of 1 0 1 0, with serial data output.

Timing Diagram Example

An example shows the transition from parallel to serial, where an initial parallel load (1110) with Clock and Load inputs leads to a serial data stream from Q4 of 1011 after each clock pulse.

• Load new data (1101) to flip-flops

Serial-to-Parallel Converter

• Converts serial data input into parallel data output.

Operation

1. Serial Data In

2. Parallel Data Out

3. Serial data is shifted into the register with each clock pulse.

4. After all data bits are shifted in, the parallel data is available at the outputs (P1, P2, P3, P4).

Example

• Serial Data In: 1 0 1 1

• After four clock cycles, the parallel data out is P4, P3, P2, P1.

• Parallel data out: p4, p3, p2, p1

Sequence Generators

• The output from the last Flip-Flop is fed back into the first Flip- Flops DIN or data input to create a feedback circuit

• Instead the data being shifted out and loosing it, we can recirculate it round

• Data that is recirculated will remain forever being cycled round

• Therefore we can produce a repeating sequence in this way

4-bit sequence generator

The lecture illustrates a 4-bit sequence generator using a feedback loop from the output of the last flip-flop (Q4) connected to the input of the first flip-flop (D1). An example depicts the states of Q1, Q2, Q3, and Q4 over several clock cycles, demonstrating the repeating sequence.

Summary

Circuit diagrams, timing diagrams and operations of:

• Data Registers

• Shift registers

• Divide-by-two operation

• Parallel-to-serial converter

• Serial-to-parallel converter

• Sequence generators