Detailed Study Notes on Computer Architecture and Control Unit

BCSE205L Computer Architecture and Organization

Module 3 – Instruction Sets and Control Unit

Introduction

• Instructor: Prof. S. Naveen Kumar

• Affiliation: School of Computer Science and Engineering, Vellore Institute of Technology, Vellore

Computer Instructions

Instruction Sets

• Definition:

  • An instruction is a statement by which the operation of the CPU is determined.

  • Machine instructions or computer instructions guide CPU operations.

Elements of Machine Instruction

• Operation Code (Opcode)

• Source Operand Reference

• Result Operand Reference

• Next Instruction Reference

Program

• A program is a sequence of instructions operating on data to perform specific tasks.

• Additional component: Instruction Cycle

Instruction Set Architecture (ISA)

• Defines how the CPU is controlled by software.

• Functions of ISA:

  • Acts as an interface between hardware and software.

  • Specifies:

  • Supported data types

  • Register functions

  • Main memory management

  • Features such as virtual memory

  • Callable instructions by the microprocessor

  • Input/output model of different implementations

Instruction Formats

• Each instruction is represented as a sequence of bits and is divided into two primary fields:

  • Opcode Field

  • Operand Field (Which may be further divided into one to four fields)

• This layout is termed the Instruction Format.

Simple Instruction Format

Categories of Instruction Sets

Based on Operations Performed

Data Movement / Transfer Instructions

• Moves data without altering its form. Types include:

  • Memory ↔ Processor Registers

  • Processor Registers ↔ I/O Devices

  • Processor Registers ↔ Processor Registers

  • Operations:

  • Load: Transfer from memory to register

  • Store: Transfer from register to memory

  • Move: Transfer between registers

  • Exchange: Swaps information

  • Input/Output: Transfers data between registers and I/O devices

  • Push/Pop: Transfer data to/from memory stack.

Data Processing / Manipulation Instructions

• These include ALU instructions affecting data forms and producing results stored elsewhere.

  • Types:

  • Arithmetic

  • Logic

  • Bit Manipulation

  • Shift Instructions

Instruction Set Category Details

Logical and Bit Manipulation Instructions

| Disable interrupt | DI |

Shift Instructions

Data Processing Instruction Details

Examples of Shifting Operations

• Logical Shift Left (e.g. 00011010 evolves as):

  • 00011010 (original) → 00110100 (shifted by 1) → 01101000 → 11010000

• Logical Shift Right (e.g. 00011010 evolves as):

  • 00011010 → 00001101 → 00000110 → 00000011

• Arithmetic Shift Left (e.g. 00011010):

  • Shifts bits while preserving sign bit. Overflow noted when sign bit changes.

• Arithmetic Shift Right (e.g. 10011010):

  • Preserves significant bits and operates differently from logical shifts.

Flow Control / Program Control

• Any instructions altering normal execution flow:

  • Conditional Jump (Conditions such as JNZ, JZ)

  • Unconditional Jump Instructions and their operation:

  • Jump to subroutine

  • Jump to the specified address

  • Replace PC contents

  • Skip instructions or halt program execution

Operand Addressing in Instruction Sets

Instruction Set Categorization by Number of Operand Addresses

• 4-Address, 3-Address, 2-Address, 1-Address, 0-Address Instruction Types.

Example for 3-Address Instruction

• Representation: X = (A + B) * (C + D)

  • Detailed steps for encoding in registers, resulting in register manipulations.

Example for 2-Address Instruction

• Representation: Similar operation encoded using fewer registers and moving results back to memory.

Example for 1-Address Instruction

• Mentioned that explicit registers aren’t typically used directly (utilizes impact on the accumulator).

Zero Address Instructions

• Operate with implicit stacks.

Memory Traffic Calculation

• Assumptions about instruction sizes and memory references tailored to operands and results. Calculations detail scenarios with various address types.

Instruction Cycle

Phases of the Instruction Cycle

• Two Phases:

  • Fetch: CPU retrieves instruction/data from RAM.

  • Execute: ALU performs operations on data.

Detailed Steps in Instruction Cycle Phases

1. Fetch Instruction: Locate and load instruction into registers.

2. Decode Instruction: Control unit decodes the instruction for actions.

3. Execute Operations: Specific operations as indicated in fetched instruction.

4. Store Result: Save processed data back into RAM or registers.

ALU (Arithmetic Logic Unit)

Overview

• Division: Comprised of an Arithmetic Unit (AU) and a Logic Unit (LU).

• Inputs and outputs process directly through buses connecting the AU, registers, and memory.

ALU Operations

• Logical Operations (AND, OR, NOT, etc.)

• Bit-Shifting Operations

• Arithmetic Operations (Addition/Subtraction).

Control Unit (CU)

• Divided into two control approaches: Hardwired and Microprogrammed control. Control units manage data flow and operating signals for ALU operations.

Hardwired Control Characteristics

• Speed and lack of flexibility, counter-driven operation. Depend on direct wiring of logic circuits.

Microprogrammed Control Characteristics

• Involves storing sequences (micro-routines) to handle complex instructions.

Performance Metrics

Execution Time and Metric Calculation

• Focus on establishing performance conditions and benchmarks through execution time calculations, including MIPS (Million Instructions Per Second) and MFLOPS (Million Floating Point Operations per Second).

Processor Performance Equation

• Related to Execution Time: Controlled by instruction counts multiplied by cycle operation times, adaptable through various instruction efficiency metrics.

http://… (Continue formatting sections as necessary with detailed notes on examples demonstrating how to use MIPS, performance evaluations under different scenarios, further addressing modes and their significance, etc.)