Chapter 7 - Input/Output and Storage Systems - Chapter 7
Chapter 7 Objectives
- Understand how I/O systems work, including I/O methods and architectures.
- Chapters 7.1 – 7.5
7.1 Introduction
- Data storage and retrieval is one of the primary functions of computer systems.
- One could easily argue that computers are more useful to us as data storage and retrieval devices than merely as computational machines.
- All computers have I/O devices connected to them, and for optimal performance, I/O should be minimized.
- In studying I/O, the focus is on understanding:
- Different types of I/O devices.
- How these devices operate.
- Sluggish I/O throughput can negatively affect overall system performance.
- This effect is particularly pronounced when virtual memory is involved.
- The fastest processor in the world is ineffective if it spends most of its time waiting for data.
- A deep understanding of what happens within a computer system enables efficient resource utilization.
7.3 Amdahl’s Law
- The overall performance of a system results from the interaction of all its components.
- System performance improvements are most effectively achieved by enhancing the performance of the most heavily used components.
- Amdahl’s Law is expressed as:
S=(1−f)+kf1
where:
- S is the overall speedup,
- f is the fraction of work performed by a faster component,
- k is the speedup of the faster component.
7.3 Amdahl’s Law (Cont.)
- Amdahl’s Law provides a method to estimate expected performance improvement from system component upgrades.
- Example Scenario:
- Upgrade CPU to be 50% faster for $10,000 or upgrade disk drives to be 150% faster for $7,000.
- Processes spend 70% of their time running in the CPU and 30% waiting for disk service.
- Determining which upgrade offers the greater benefit for the lesser cost:
- CPU upgrade yields a 30% speedup.
- Disk drive upgrade results in a 22% speedup.
- Cost analysis:
- For processor improvement: each 1% improvement costs $333.
- For disk improvement: each 1% improvement costs $318.
- Should price/performance be the only concern?
7.4 I/O Architectures
- I/O is a subsystem of components that moves coded data between external devices and the host system.
- I/O subsystems include:
- Blocks of main memory for I/O functions.
- Buses that facilitate data movement into and out of the system.
- Control modules located in both the host and peripheral devices.
- Interfaces to external components such as keyboards and storage devices.
- Cabling or communication links connecting the host system to its peripherals.
7.4 I/O Architectures (Visual Representation)
- A model I/O configuration includes:
- Main memory, CPU, motherboard, I/O bus, monitor, I/O modules, device interfaces, device adapters, and control electronics.
7.4 I/O Control Methods
- I/O can be managed in five general ways:
- Programmed I/O:
- Reserves a register for each I/O device and continually polls each register to detect data arrival.
- Interrupt-Driven I/O:
- Allows CPU to perform other tasks until I/O requests arise.
- Memory-Mapped I/O:
- Shares the memory address space between I/O devices and program memory, simplifying data transfer processes.
- Direct Memory Access (DMA):
- Offloads I/O processing to a specialized chip that manages the transfer details without CPU intervention.
- Channel I/O:
- Utilizes dedicated I/O processors (IOPs) to handle various channels of data flow.
7.4 I/O Architectures (Interrupt Handling)
- In interrupt-driven I/O, the interrupt controller signals the CPU when any of the interrupt lines are asserted.
- The status of the interrupt signal is checked at the top of the fetch-decode-execute cycle.
- A specific code defined by addresses (interrupt vectors) stored in low memory executes when an interrupt occurs.
- Before executing the interrupt service routine (ISR), the system state is saved and restored post-execution.
7.4 I/O Architectures (Flowchart of Interrupt Process)
- Steps in the flowchart for handling interrupts:
- Start when interrupt signal detected.
- Place ISR address into the Program Counter (PC).
- Save current variables and registers.
- Look up ISR address in the interrupt vector table.
- Branch to ISR to execute necessary code.
- Restore any saved registers and variables.
- Branch back to the top of the fetch-decode-execute cycle to resume processing.
7.4 I/O Architectures (Memory-mapped I/O)
- Memory-mapped I/O means I/O devices coexist in the same address space as main memory:
- Each I/O device has a designated block of memory.
- This technique requires the same instructions to move data to and from both I/O and memory, making it easier for system design.
- In smaller systems, low-level data transfer details are managed by I/O controllers built into devices.
7.4 I/O Architectures (DMA Configuration)
- In the DMA configuration, the DMA shares the bus with the CPU but operates with higher priority and can access memory cycles from the CPU.
7.4 I/O Architectures (Channel I/O)
- Very large systems often implement channel I/O, which employs one or more I/O processors (IOPs) for channel management.
- Slower devices like terminals and printers are multiplexed into a single faster channel.
- In IBM mainframes, multiplexed channels are termed 'multiplexor channels' while the faster channels are referred to as 'selector channels.'
- The IOP governs protocols, issues device commands, translates between storage and memory coding, and can handle file transfers independently of the CPU.
7.4 I/O Architectures (Channel I/O Configuration)
- A generic illustration of a channel I/O configuration includes:
- Main memory, CPU, I/O processors (IOPs), various devices, and the local area network.
7.4 I/O Architectures (DMA Circuit)
- Configuration of a generic DMA showing how DMA circuits connect to a data bus.
Chapter 7 Conclusion
- I/O systems are crucial to a computer system's overall performance.
- Amdahl’s Law serves as a quantitative measure of this assertion.
- I/O systems encompass memory blocks, cabling, control circuitry, interfaces, and media.
- Control methods for managing I/O include programmed I/O, interrupt-based I/O, DMA, and channel I/O.