Diode Applications: Rectifiers, Filters, and Zener Voltage Regulators

Regulated Power Supply Architecture and Block Diagram

  • A regulated DC power supply converts an alternating current (AC) line voltage into a constant, ripple-free direct current (DC) voltage that remains stable despite fluctuations in input line voltage or output load resistance.

Block diagram of a regulated DC power supply with intermediate waveforms
  • Transformer:

    • Steps up or steps down the incoming AC line sinusoidal voltage (vi=Vmsin⁡(ωt)v_i = V_m \sin(\omega t)) to the desired voltage level.

    • Provides electrical isolation between the high-voltage commercial AC mains and the electronic circuit components.

  • Rectifier:

    • A diode-based circuit that converts the bidirectional AC sinusoidal waveform into a unidirectional pulsating DC signal.

    • Allows current to pass in one direction while blocking current flow in the reverse direction.

  • Filter:

    • Suppresses and attenuates the AC ripple components present in the pulsating DC output.

    • Smoothes the output into a DC level with minimal time-dependent fluctuation.

  • Regulator:

    • Eliminates residual ripple and maintains a strictly constant output DC voltage (VoutV_{\text{out}}) across the load despite variations in the input line voltage or the load current (IoutI_{\text{out}}).

Rectifier Classifications and Circuit Configurations

  • Rectifiers are classified based on the portion of the alternating input cycle they conduct to the load.

Classification and circuit schematics of rectifiers
  • Half-Wave Rectifier (HWR):

    • Conducts current to the load only during either the positive or negative half-cycle of the AC input, blocking conduction during the complementary half-cycle.

    • Utilizes a single diode in series with the load resistor.

  • Full-Wave Rectifier (FWR):

    • Conducts current to the load in the same direction during both the positive and negative half-cycles of the AC input voltage.

    • Center-Tapped Full-Wave Rectifier: Utilizes a center-tapped secondary transformer winding and two diodes (D1D_1 and D2D_2).

    • Full-Wave Bridge Rectifier: Utilizes four diodes arranged in a bridge loop (D1,D2,D3,D4D_1, D_2, D_3, D_4) across a standard transformer secondary winding.

Half-Wave Rectification (HWR) Theory and Derivations

Conduction Cycle with Ideal Diode in a Half-Wave Rectifier consists of a single diode conducting during one half of the input AC cycle while blocking the other half, resulting in a pulsating DC output. This process can be illustrated through the waveform analysis, showing the output voltage transitioning between zero and the peak input voltage during the conduction phase, creating a series of half cycles that can be smoothed with additional filtering. In this method, the diode operates in a forward bias state during the positive half-cycle, allowing current to flow, while during the negative half-cycle it becomes reverse biased and effectively stops current, thereby producing an output that can be represented as a series of positive peaks corresponding to the input AC voltage.

Conduction path of an ideal diode half-wave rectifier during the positive half-cycle
  • Positive Half-Cycle (0≤ωt≤π0 \le \omega t \le \pi):

    • The anode is positive relative to the cathode, forward-biasing the diode.

    • The diode functions as a closed switch (short circuit with Vd=0 VV_d = 0\,\text{V}).

    • The load voltage follows the input waveform: vo=viv_o = v_i.

    • Peak load voltage: Vo,max=VmV_{o,\text{max}} = V_m.

    • Current through the load: iL=viRLi_L = \frac{v_i}{R_L}, with peak value Im=VmRLI_m = \frac{V_m}{R_L}.

  • Negative Half-Cycle (π≤ωt≤2π\pi \le \omega t \le 2\pi):

    • The polarity of the input signal reverses, placing the diode in reverse bias.

    • The diode functions as an open switch (iL=0 Ai_L = 0\,\text{A}).

    • The load voltage is zero: vo=iLRL=(0)RL=0 Vv_o = i_L R_L = (0) R_L = 0\,\text{V}.

Mathematical Derivations for Ideal HWR

Input and output waveforms showing the DC average voltage in a half-wave rectifier
  • Average (DC) Voltage (VdcV_{\text{dc}}):

    • Evaluated by integrating the rectified waveform over the full period (2π2\pi):   Vdc=12π∫02πVmsin⁡(ωt) d(ωt)=12π∫0πVmsin⁡(ωt) d(ωt)V_{\text{dc}} = \frac{1}{2\pi} \int_0^{2\pi} V_m \sin(\omega t)\,d(\omega t) = \frac{1}{2\pi} \int_0^\pi V_m \sin(\omega t)\,d(\omega t)   Vdc=Vm2π[−cos⁡(ωt)]0π=Vm2π[−(−1)−(−1)]=Vmπ≈0.318 VmV_{\text{dc}} = \frac{V_m}{2\pi} \left[ -\cos(\omega t) \right]_0^\pi = \frac{V_m}{2\pi} [ -(-1) - (-1) ] = \frac{V_m}{\pi} \approx 0.318\,V_m

  • Average (DC) Current (IdcI_{\text{dc}}):   Idc=VdcRL=VmπRL=Imπ≈0.318 ImI_{\text{dc}} = \frac{V_{\text{dc}}}{R_L} = \frac{V_m}{\pi R_L} = \frac{I_m}{\pi} \approx 0.318\,I_m

  • Root Mean Square (RMS) Voltage (VrmsV_{\text{rms}}):

    • Evaluated across the complete period (2π2\pi):   Vrms=[12π∫0π(Vmsin⁡(ωt))2 d(ωt)]1/2V_{\text{rms}} = \left[ \frac{1}{2\pi} \int_0^\pi (V_m \sin(\omega t))^2\,d(\omega t) \right]^{1/2}   Vrms=[Vm22π∫0π1−cos⁡(2ωt)2 d(ωt)]1/2V_{\text{rms}} = \left[ \frac{V_m^2}{2\pi} \int_0^\pi \frac{1 - \cos(2\omega t)}{2}\,d(\omega t) \right]^{1/2}   Vrms=[Vm24π[ωt−sin⁡(2ωt)2]0π]1/2=[Vm24π(π−0)]1/2=Vm2=0.5 VmV_{\text{rms}} = \left[ \frac{V_m^2}{4\pi} \left[ \omega t - \frac{\sin(2\omega t)}{2} \right]_0^\pi \right]^{1/2} = \left[ \frac{V_m^2}{4\pi} (\pi - 0) \right]^{1/2} = \frac{V_m}{2} = 0.5\,V_m

  • Root Mean Square (RMS) Current (IrmsI_{\text{rms}}):   Irms=VrmsRL=Vm2RL=Im2=0.5 ImI_{\text{rms}} = \frac{V_{\text{rms}}}{R_L} = \frac{V_m}{2 R_L} = \frac{I_m}{2} = 0.5\,I_m

Practical (Non-Ideal) Diode Considerations

Effect of diode threshold voltage on a half-wave rectified waveform
  • When incorporating the knee/offset voltage (VkV_k or VT=0.7 VV_T = 0.7\,\text{V} for silicon):

    • Conduction begins only when vi>Vkv_i > V_k.

    • Peak load voltage: Vo,max=Vm−VkV_{o,\text{max}} = V_m - V_k.

    • Peak load current: Im=Vm−VkRLI_m = \frac{V_m - V_k}{R_L}.

    • Average DC output voltage: Vdc=Vm−Vkπ≈0.318(Vm−Vk)V_{\text{dc}} = \frac{V_m - V_k}{\pi} \approx 0.318(V_m - V_k).

    • Average DC current: Idc=Vm−VkπRL=ImπI_{\text{dc}} = \frac{V_m - V_k}{\pi R_L} = \frac{I_m}{\pi}.

    • RMS output voltage: Vrms=Vm−Vk2V_{\text{rms}} = \frac{V_m - V_k}{2}.

    • RMS load current: Irms=Vm−Vk2RL=Im2I_{\text{rms}} = \frac{V_m - V_k}{2 R_L} = \frac{I_m}{2}.

Peak Inverse Voltage (PIV) of HWR the total voltage drop is across the diode

Peak Inverse Voltage determination in a half-wave rectifier during the negative half-cycle
  • Definition: Peak Inverse Voltage (PIV) or Peak Reverse Voltage (PRV) is the maximum instantaneous reverse bias voltage that develops across the non-conducting diode without causing junction breakdown.

  • Applying Kirchhoff's Voltage Law (KVL) around the loop during the negative half-cycle with peak reverse input VmV_m:   −Vm+PIV−vo=0-V_m + \text{PIV} - v_o = 0

  • Since iL=0 Ai_L = 0\,\text{A}, vo=0 Vv_o = 0\,\text{V}, leading directly to:   PIV≥Vm\text{PIV} \ge V_m

Ripple Factor and Output Frequency of HWR

  • Ripple Factor (γ\gamma): Measure of the residual AC fluctuation relative to the DC component:   γ=Vrms′Vdc\gamma = \frac{V'_{\text{rms}}}{V_{\text{dc}}}

    • The total RMS voltage contains both AC and DC components: Vrms2=(Vrms′)2+Vdc2V_{\text{rms}}^2 = (V'_{\text{rms}})^2 + V_{\text{dc}}^2.

    • The RMS value of the AC ripple component is:   Vrms′=Vrms2−Vdc2=(Vm2)2−(Vmπ)2=0.385 VmV'_{\text{rms}} = \sqrt{V_{\text{rms}}^2 - V_{\text{dc}}^2} = \sqrt{\left(\frac{V_m}{2}\right)^2 - \left(\frac{V_m}{\pi}\right)^2} = 0.385\,V_m

    • Substituting into the ripple factor equation:   γHWR=(VrmsVdc)2−1=(Vm/2Vm/π)2−1=(π2)2−1=2.4674−1≈1.21\gamma_{\text{HWR}} = \sqrt{\left( \frac{V_{\text{rms}}}{V_{\text{dc}}} \right)^2 - 1} = \sqrt{\left( \frac{V_m / 2}{V_m / \pi} \right)^2 - 1} = \sqrt{\left( \frac{\pi}{2} \right)^2 - 1} = \sqrt{2.4674 - 1} \approx 1.21

  • Output Frequency:

    • The period of one complete output rectified waveform is identical to the input waveform period (To=TiT_o = T_i):   fo=fif_o = f_i

Full-Wave Rectification: Center-Tapped and Bridge Configurations

Center-Tapped Full-Wave Rectifier

Center-tapped full-wave rectifier schematic and transformer secondary voltages
  • Requires a center-tapped transformer providing two equal secondary out-of-phase voltages (vAC=vCB=vi=Vmsin⁡(ωt)v_{AC} = v_{CB} = v_i = V_m \sin(\omega t)).

Conduction path and output voltage of center-tapped rectifier during the positive half-cycle
  • Positive Half-Cycle (0≤ωt≤π0 \le \omega t \le \pi):

    • Upper terminal AA is positive with respect to the center tap CTCT, while bottom terminal BB is negative.

    • Diode D1D_1 is forward-biased ("on"); diode D2D_2 is reverse-biased ("off").

    • Current flows through D1D_1, through RLR_L from right to left, returning to CTCT.

    • Output voltage: vo=viv_o = v_i, with Vo,max=VmV_{o,\text{max}} = V_m.

  • Negative Half-Cycle (π≤ωt≤2π\pi \le \omega t \le 2\pi):

    • Lower terminal BB becomes positive with respect to CTCT, while upper terminal AA becomes negative.

    • Diode D1D_1 is reverse-biased ("off"); diode D2D_2 is forward-biased ("on").

    • Current flows through D2D_2, entering the load resistor RLR_L in the identical direction (right to left).

    • Output voltage: vo=−viv_o = -v_i, with Vo,max=VmV_{o,\text{max}} = V_m.

  • Center-Tapped PIV Requirement:

    • When D1D_1 conducts, terminal AA is at +Vm+V_m, terminal CTCT is at 0 V0\,\text{V}, and terminal BB is at −Vm-V_m.

    • Loop voltage across non-conducting diode D2D_2:   PIV=Vsecondary+VR=Vm+Vm=2Vm\text{PIV} = V_{\text{secondary}} + V_R = V_m + V_m = 2V_m

  • Accounting for diode offset voltage VkV_k:   PIV≥2Vm−Vk\text{PIV} \ge 2V_m - V_k


Full-Wave Bridge Rectifier

Full-wave bridge rectifier topology and conduction states during positive input half-cycle
  • Employs four diodes (D1,D2,D3,D4D_1, D_2, D_3, D_4) without requiring a center-tapped transformer.

  • Positive Half-Cycle (0→T/20 \to T/2):

    • Top input terminal is positive; bottom input terminal is negative.

    • Diodes D2D_2 and D3D_3 are forward-biased ("on"); diodes D1D_1 and D4D_4 are reverse-biased ("off").

    • Conduction path: Input positive rail →D2→RL→D3→\rightarrow D_2 \rightarrow R_L \rightarrow D_3 \rightarrow input negative rail.

    • Load voltage: vo=viv_o = v_i, with peak Vo,max=VmV_{o,\text{max}} = V_m.

Full-wave bridge rectifier equivalent conduction path during negative input half-cycle
  • Negative Half-Cycle (T/2→TT/2 \to T):

    • Bottom input terminal is positive; top input terminal is negative.

    • Diodes D1D_1 and D4D_4 are forward-biased ("on"); diodes D2D_2 and D3D_3 are reverse-biased ("off").

    • Conduction path: Input bottom positive terminal →D4→RL→D1→\rightarrow D_4 \rightarrow R_L \rightarrow D_1 \rightarrow input top negative terminal.

    • Current passes through the load in the identical direction, maintaining unipolar output.

Full-wave bridge rectifier practical diode model showing two diode drops
  • Practical Diode Considerations for Bridge Rectifier:

    • Two diodes conduct simultaneously in series with the load during each half-cycle.

    • Applying KVL around the active loop:   vi−Vk−vo−Vk=0v_i - V_k - v_o - V_k = 0   vo=vi−2Vkv_o = v_i - 2V_k   Vo,max=Vm−2VkV_{o,\text{max}} = V_m - 2V_k

  • Bridge Rectifier PIV Requirement:

    • Ideal diodes: PIV−Vm=0  ⟹  PIV≥Vm\text{PIV} - V_m = 0 \implies \text{PIV} \ge V_m

    • Non-ideal diodes: PIV−Vk−vo=0  ⟹  PIV=vo+Vk=(Vm−2Vk)+Vk  ⟹  PIV≥Vm−Vk\text{PIV} - V_k - v_o = 0 \implies \text{PIV} = v_o + V_k = (V_m - 2V_k) + V_k \implies \text{PIV} \ge V_m - V_k

Mathematical Derivations for Ideal FWR

  • Average (DC) Voltage (VdcV_{\text{dc}}):   Vdc=1π∫0πVmsin⁡(ωt) d(ωt)=Vmπ[−cos⁡(ωt)]0π=2Vmπ≈0.636 VmV_{\text{dc}} = \frac{1}{\pi} \int_0^\pi V_m \sin(\omega t)\,d(\omega t) = \frac{V_m}{\pi} \left[ -\cos(\omega t) \right]_0^\pi = \frac{2V_m}{\pi} \approx 0.636\,V_m

  • Average (DC) Current (IdcI_{\text{dc}}):   Idc=VdcRL=2VmπRL=2Imπ≈0.636 ImI_{\text{dc}} = \frac{V_{\text{dc}}}{R_L} = \frac{2V_m}{\pi R_L} = \frac{2I_m}{\pi} \approx 0.636\,I_m

  • Root Mean Square (RMS) Voltage (VrmsV_{\text{rms}}):   Vrms=[1π∫0π(Vmsin⁡(ωt))2 d(ωt)]1/2=[Vm22π∫0π(1−cos⁡(2ωt)) d(ωt)]1/2V_{\text{rms}} = \left[ \frac{1}{\pi} \int_0^\pi (V_m \sin(\omega t))^2\,d(\omega t) \right]^{1/2} = \left[ \frac{V_m^2}{2\pi} \int_0^\pi (1 - \cos(2\omega t))\,d(\omega t) \right]^{1/2}   Vrms=[Vm22π(π−0)]1/2=Vm2≈0.707 VmV_{\text{rms}} = \left[ \frac{V_m^2}{2\pi} (\pi - 0) \right]^{1/2} = \frac{V_m}{\sqrt{2}} \approx 0.707\,V_m

  • Root Mean Square (RMS) Current (IrmsI_{\text{rms}}):   Irms=VrmsRL=Vm2RL=Im2≈0.707 ImI_{\text{rms}} = \frac{V_{\text{rms}}}{R_L} = \frac{V_m}{\sqrt{2} R_L} = \frac{I_m}{\sqrt{2}} \approx 0.707\,I_m

  • Ripple Factor (γFWR\gamma_{\text{FWR}}):   Vrms′=Vrms2−Vdc2=(Vm2)2−(2Vmπ)2=0.5−0.4053 Vm=0.307 VmV'_{\text{rms}} = \sqrt{V_{\text{rms}}^2 - V_{\text{dc}}^2} = \sqrt{\left(\frac{V_m}{\sqrt{2}}\right)^2 - \left(\frac{2V_m}{\pi}\right)^2} = \sqrt{0.5 - 0.4053}\,V_m = 0.307\,V_m   γFWR=(VrmsVdc)2−1=(Vm/22Vm/π)2−1=π28−1=1.2337−1≈0.48\gamma_{\text{FWR}} = \sqrt{\left( \frac{V_{\text{rms}}}{V_{\text{dc}}} \right)^2 - 1} = \sqrt{\left( \frac{V_m / \sqrt{2}}{2V_m / \pi} \right)^2 - 1} = \sqrt{\frac{\pi^2}{8} - 1} = \sqrt{1.2337 - 1} \approx 0.48

  • Output Frequency:

    • The output waveform repeats every T/2T/2 intervals: To=Ti2T_o = \frac{T_i}{2}.   fo=2fif_o = 2 f_i

Performance Metrics and Comparative Analysis of Rectifiers

Master Parameter Comparison Table

Parameter

HWR (Ideal)

HWR (Practical)

Center-Tapped FWR (Ideal)

Center-Tapped FWR (Practical)

Bridge FWR (Ideal)

Bridge FWR (Practical)

IdcI_{\text{dc}}

Imπ\frac{I_m}{\pi}

Imπ\frac{I_m}{\pi}

2Imπ\frac{2I_m}{\pi}

2Imπ\frac{2I_m}{\pi}

2Imπ\frac{2I_m}{\pi}

2Imπ\frac{2I_m}{\pi}

VdcV_{\text{dc}}

Vmπ\frac{V_m}{\pi}

Vm−Vkπ\frac{V_m - V_k}{\pi}

2Vmπ\frac{2V_m}{\pi}

2(Vm−Vk)π\frac{2(V_m - V_k)}{\pi}

2Vmπ\frac{2V_m}{\pi}

2(Vm−2Vk)π\frac{2(V_m - 2V_k)}{\pi}

IrmsI_{\text{rms}}

Im2\frac{I_m}{2}

Im2\frac{I_m}{2}

Im2\frac{I_m}{\sqrt{2}}

Im2\frac{I_m}{\sqrt{2}}

Im2\frac{I_m}{\sqrt{2}}

Im2\frac{I_m}{\sqrt{2}}

VrmsV_{\text{rms}}

Vm2\frac{V_m}{2}

Vm−Vk2\frac{V_m - V_k}{2}

Vm2\frac{V_m}{\sqrt{2}}

Vm−Vk2\frac{V_m - V_k}{\sqrt{2}}

Vm2\frac{V_m}{\sqrt{2}}

Vm−2Vk2\frac{V_m - 2V_k}{\sqrt{2}}

Peak Inverse Voltage (PIV)

VmV_m

VmV_m

2Vm2V_m

2Vm−Vk2V_m - V_k

VmV_m

Vm−VkV_m - V_k

Ripple Factor (γ\gamma)

1.211.21

1.211.21

0.480.48

0.480.48

0.480.48

0.480.48

Output Frequency (fof_o)

fif_i

fif_i

2fi2f_i

2fi2f_i

2fi2f_i

2fi2f_i

Systematic Differences: Center-Tapped vs. Bridge Rectifier

  • Peak Inverse Voltage: Bridge rectifier requires a PIV rating of only VmV_m, whereas a center-tapped rectifier requires twice as much (2Vm2V_m).

  • Transformer Complexity: Center-tapped configuration mandates an expensive and bulky center-tapped transformer; the bridge rectifier functions with a conventional two-wire secondary winding.

  • Secondary Balance: Balancing the voltages on both halves of a center-tapped secondary winding is difficult; bridge rectifiers provide an inherently uniform input voltage across both half-cycles.

  • Diode Count: Center-tapped rectifiers require 2 diodes; bridge rectifiers require 4 diodes.

  • Internal Conduction Loss: Center-tapped rectifiers exhibit a lower forward drop (Vk=0.7 VV_k = 0.7\,\text{V}) due to one conducting diode per half-cycle; bridge rectifiers introduce a larger forward drop (2Vk=1.4 V2V_k = 1.4\,\text{V}) due to two conducting diodes in series.

Rectifier Analysis: Worked Numerical Examples

Example 1: Half-Wave Rectifier Analysis (Ideal vs. Silicon Diode)

  • Problem Statement: A half-wave rectifier has a sinusoidal input of frequency 60 Hz60\,\text{Hz} and a load resistor R=2.2 kΩR = 2.2\,\text{k}\Omega. The DC output voltage is measured as Vdc=2 VV_{\text{dc}} = 2\,\text{V}. Determine the required input peak voltage VmV_m, peak load current ImI_m, and sketch the waveforms for (a) an ideal diode and (b) a silicon diode with Vk=0.7 VV_k = 0.7\,\text{V}.

  • Solution for Part (a) - Ideal Diode:

    • Using the ideal average voltage relationship:   Vdc=0.318 Vm  ⟹  Vm=Vdc0.318=2 V0.318=6.28 VV_{\text{dc}} = 0.318\,V_m \implies V_m = \frac{V_{\text{dc}}}{0.318} = \frac{2\,\text{V}}{0.318} = 6.28\,\text{V}

    • Peak diode and load current:   Im=VmR=6.28 V2.2 kΩ=2.85 mAI_m = \frac{V_m}{R} = \frac{6.28\,\text{V}}{2.2\,\text{k}\Omega} = 2.85\,\text{mA}

    • Peak inverse voltage appearing across diode in reverse bias: vd=−6.28 Vv_d = -6.28\,\text{V}.

  • Solution for Part (b) - Silicon Diode (Vk=0.7 VV_k = 0.7\,\text{V}):

    • Using the practical average voltage relationship:   Vdc=0.318(Vm−Vk)=0.318(Vm−0.7 V)=2 VV_{\text{dc}} = 0.318(V_m - V_k) = 0.318(V_m - 0.7\,\text{V}) = 2\,\text{V}   Vm−0.7 V=2 V0.318=6.28 V  ⟹  Vm=6.28 V+0.7 V=6.98 VV_m - 0.7\,\text{V} = \frac{2\,\text{V}}{0.318} = 6.28\,\text{V} \implies V_m = 6.28\,\text{V} + 0.7\,\text{V} = 6.98\,\text{V}

    • Peak load voltage: VR,peak=Vm−Vk=6.98 V−0.7 V=6.28 VV_{R,\text{peak}} = V_m - V_k = 6.98\,\text{V} - 0.7\,\text{V} = 6.28\,\text{V}.

    • Peak conduction current:   Im=Vm−VkR=6.28 V2.2 kΩ=2.85 mAI_m = \frac{V_m - V_k}{R} = \frac{6.28\,\text{V}}{2.2\,\text{k}\Omega} = 2.85\,\text{mA}

    • Peak diode reverse voltage: vd=−Vm=−6.98 Vv_d = -V_m = -6.98\,\text{V}.

Example 2: Parallel Diode Protection in Half-Wave Rectifier

  • Problem Statement: A half-wave rectifier is driven by a peak input voltage Vi,max=160 VV_{i,\text{max}} = 160\,\text{V}. The load consists of two parallel resistors: 4.7 kΩ∥56 kΩ4.7\,\text{k}\Omega \parallel 56\,\text{k}\Omega. Each diode has a maximum power dissipation rating Pmax=14 mWP_{\text{max}} = 14\,\text{mW} and an offset voltage Vk=0.7 VV_k = 0.7\,\text{V}.

    • (a) Determine the maximum current rating IDI_D for each diode.

    • (b) Calculate the total peak load current ImaxI_{\text{max}}.

    • (c) Calculate the current passing through each diode when two diodes are connected in parallel.

    • (d) Evaluate the circuit performance if only a single diode is used.

  • Solution:

    • Part (a): Maximum diode current rating:   Pmax=VkID  ⟹  ID=PmaxVk=14 mW0.7 V=20 mAP_{\text{max}} = V_k I_D \implies I_D = \frac{P_{\text{max}}}{V_k} = \frac{14\,\text{mW}}{0.7\,\text{V}} = 20\,\text{mA}

    • Part (b): Total equivalent load resistance:   RL=4.7 kΩ∥56 kΩ=4.7×564.7+56 kΩ=4.34 kΩR_L = 4.7\,\text{k}\Omega \parallel 56\,\text{k}\Omega = \frac{4.7 \times 56}{4.7 + 56}\,\text{k}\Omega = 4.34\,\text{k}\Omega

    • Peak voltage across load:   VR=Vi,max−Vk=160 V−0.7 V=159.3 VV_R = V_{i,\text{max}} - V_k = 160\,\text{V} - 0.7\,\text{V} = 159.3\,\text{V}

    • Total maximum loop current:   Imax=VRRL=159.3 V4.34 kΩ=36.71 mAI_{\text{max}} = \frac{V_R}{R_L} = \frac{159.3\,\text{V}}{4.34\,\text{k}\Omega} = 36.71\,\text{mA}

    • Part (c): Current per diode with two parallel identical diodes:   Idiode=Imax2=36.71 mA2=18.36 mAI_{\text{diode}} = \frac{I_{\text{max}}}{2} = \frac{36.71\,\text{mA}}{2} = 18.36\,\text{mA}

    • Since 18.36 mA<ID=20 mA18.36\,\text{mA} < I_D = 20\,\text{mA}, the diodes operate safely within thermal limits.

    • Part (d): Single diode condition:   Idiode=Imax=36.71 mA≫20 mAI_{\text{diode}} = I_{\text{max}} = 36.71\,\text{mA} \gg 20\,\text{mA}

    • Exceeding the maximum rating leads to excessive thermal dissipation and total destruction of the diode.

Example 3: Bridge Circuit with Resistor Arms

  • Problem Statement: A bridge configuration contains two ideal diodes in the upper branches and two 2 kΩ2\,\text{k}\Omega resistors in the lower branches, with a central load resistor R=2 kΩR = 2\,\text{k}\Omega. The input is a sinusoidal voltage with peak amplitude 10 V10\,\text{V}. Determine the peak output voltage Vo,maxV_{o,\text{max}} and the DC level VdcV_{\text{dc}}.

  • Solution:

    • During the positive half-cycle, the active diode connects the positive rail to the top node. By voltage divider action between the series-parallel combination:   Vo,max=2 kΩ2 kΩ+2 kΩVi,max=12(10 V)=5 VV_{o,\text{max}} = \frac{2\,\text{k}\Omega}{2\,\text{k}\Omega + 2\,\text{k}\Omega} V_{i,\text{max}} = \frac{1}{2} (10\,\text{V}) = 5\,\text{V}

    • During the negative half-cycle, the opposite diode conducts, producing a half-cycle of identical polarity with peak amplitude 5 V5\,\text{V}.

    • The resulting output is a full-wave rectified waveform of amplitude Vm=5 VV_m = 5\,\text{V}.   Vdc=0.636 Vm=0.636(5 V)=3.18 VV_{\text{dc}} = 0.636\,V_m = 0.636(5\,\text{V}) = 3.18\,\text{V}

Example 4: Asymmetric Diode Bridge with Unequal Resistor Arms

  • Problem Statement: A bridge circuit consists of two ideal diodes on the left arms and three 2.2 kΩ2.2\,\text{k}\Omega resistors (top right, bottom right, and center load). The input voltage is vi=±170 Vv_i = \pm 170\,\text{V}. Determine the peak load voltage and the DC output level.

  • Solution:

    • Positive Pulse of viv_i:

    • Top left diode is "off", bottom left diode is "on".

    • Parallel branch resistance: 2.2 kΩ∥2.2 kΩ=1.1 kΩ2.2\,\text{k}\Omega \parallel 2.2\,\text{k}\Omega = 1.1\,\text{k}\Omega.

    • Voltage divider calculation across the load:     Vo,peak=1.1 kΩ1.1 kΩ+2.2 kΩ(170 V)=1.13.3(170 V)=56.67 VV_{o,\text{peak}} = \frac{1.1\,\text{k}\Omega}{1.1\,\text{k}\Omega + 2.2\,\text{k}\Omega} (170\,\text{V}) = \frac{1.1}{3.3} (170\,\text{V}) = 56.67\,\text{V}

    • Negative Pulse of viv_i:

    • Top left diode is "on", bottom left diode is "off".

    • Parallel combination: 2.2 kΩ∥2.2 kΩ=1.1 kΩ2.2\,\text{k}\Omega \parallel 2.2\,\text{k}\Omega = 1.1\,\text{k}\Omega.

    • Symmetrical division yields: Vo,peak=1.1 kΩ1.1 kΩ+2.2 kΩ(170 V)=56.67 VV_{o,\text{peak}} = \frac{1.1\,\text{k}\Omega}{1.1\,\text{k}\Omega + 2.2\,\text{k}\Omega} (170\,\text{V}) = 56.67\,\text{V}.

    • DC Voltage:   Vdc=0.636(56.67 V)=36.04 VV_{\text{dc}} = 0.636(56.67\,\text{V}) = 36.04\,\text{V}

Example 5: Reverse-Oriented Bridge Network

  • Problem Statement: An input vi=±100 Vv_i = \pm 100\,\text{V} is applied to a bridge rectifier where the diodes are reversed relative to ground, feeding a grounded load resistor R=2.2 kΩR = 2.2\,\text{k}\Omega. Find the output waveform polarity, peak current, and required diode PIV.

  • Solution:

    • The reversed diodes clamp the load terminal to negative potentials during both half-cycles.

    • The output is negative-going full-wave rectified pulses with peak Vo=−100 VV_o = -100\,\text{V}.

    • Peak current through each conducting diode:   Imax=100 V2.2 kΩ=45.45 mAI_{\text{max}} = \frac{100\,\text{V}}{2.2\,\text{k}\Omega} = 45.45\,\text{mA}

    • Required PIV rating for each diode:   PIV≥100 V\text{PIV} \ge 100\,\text{V}

Example 6: Full-Wave Bridge Rectifier with Commercial AC Input

  • Problem Statement: A full-wave bridge rectifier with a 120 Vrms120\,\text{V}_{\text{rms}} sinusoidal input supplies a load resistor RL=1 kΩR_L = 1\,\text{k}\Omega using silicon diodes (Vk=0.7 VV_k = 0.7\,\text{V}). Determine:

    • (a) The DC voltage available at the load.

    • (b) The required PIV rating of each diode.

    • (c) The maximum current through each diode during conduction.

    • (d) The required power rating of each diode.

  • Solution:

    • Part (a): Peak AC input voltage:   Vm=2Vrms=2(120 V)=169.7 VV_m = \sqrt{2} V_{\text{rms}} = \sqrt{2} (120\,\text{V}) = 169.7\,\text{V}

    • Peak voltage delivered to load after two diode forward drops:   VL,max=Vm−2Vk=169.7 V−2(0.7 V)=169.7 V−1.4 V=168.3 VV_{L,\text{max}} = V_m - 2V_k = 169.7\,\text{V} - 2(0.7\,\text{V}) = 169.7\,\text{V} - 1.4\,\text{V} = 168.3\,\text{V}

    • Resulting DC load voltage:   Vdc=0.636(168.3 V)=107.04 VV_{\text{dc}} = 0.636(168.3\,\text{V}) = 107.04\,\text{V}

    • Part (b): Diode PIV rating:   PIV≥Vm−Vk=169.7 V−0.7 V=169 V\text{PIV} \ge V_m - V_k = 169.7\,\text{V} - 0.7\,\text{V} = 169\,\text{V}

    • Part (c): Maximum forward conduction current:   ID(max)=VL,maxRL=168.3 V1 kΩ=168.3 mAI_D(\text{max}) = \frac{V_{L,\text{max}}}{R_L} = \frac{168.3\,\text{V}}{1\,\text{k}\Omega} = 168.3\,\text{mA}

    • Part (d): Diode maximum power rating:   Pmax=VkID(max)=(0.7 V)(168.3 mA)=117.81 mWP_{\text{max}} = V_k I_D(\text{max}) = (0.7\,\text{V})(168.3\,\text{mA}) = 117.81\,\text{mW}

Example 7: Transformer-Fed Bridge Rectifier

  • Problem Statement: An input supply v1=230sin⁡(314t) Vv_1 = 230\sin(314t)\,\text{V} is applied across the primary of a 10:110:1 step-down transformer connected to a full-wave bridge rectifier with RL=500 ΩR_L = 500\,\Omega. Determine:

    • (a) DC load voltage (VdcV_{\text{dc}}).

    • (b) RMS load voltage (VrmsV_{\text{rms}}).

    • (c) PIV rating across diodes.

    • (d) DC power delivered to the load (PdcP_{\text{dc}}).

    • (e) Output ripple frequency (fof_o).

  • Solution:

    • Input Voltage and Turns Ratio:   N1N2=101\frac{N_1}{N_2} = \frac{10}{1}   v2=N2N1v1=110(230sin⁡(314t))=23sin⁡(314t) Vv_2 = \frac{N_2}{N_1} v_1 = \frac{1}{10} (230\sin(314t)) = 23\sin(314t)\,\text{V}   Vm=23 VV_m = 23\,\text{V}

    • Input frequency: ω=314 rad/s  ⟹  fi=3142π=50 Hz\omega = 314\,\text{rad/s} \implies f_i = \frac{314}{2\pi} = 50\,\text{Hz}.

    • Part (a): DC load voltage:   Vdc=2Vmπ=2×23 Vπ=14.64 VV_{\text{dc}} = \frac{2V_m}{\pi} = \frac{2 \times 23\,\text{V}}{\pi} = 14.64\,\text{V}

    • Part (b): RMS load voltage:   Vrms=Vm2=23 V2=16.26 VV_{\text{rms}} = \frac{V_m}{\sqrt{2}} = \frac{23\,\text{V}}{\sqrt{2}} = 16.26\,\text{V}

    • Part (c): PIV across each diode:   PIV≥Vm=23 V\text{PIV} \ge V_m = 23\,\text{V}

    • Part (d): DC power delivered to load:   Pdc=Vdc2RL=(14.64 V)2500 Ω=0.428 WP_{\text{dc}} = \frac{V_{\text{dc}}^2}{R_L} = \frac{(14.64\,\text{V})^2}{500\,\Omega} = 0.428\,\text{W}

    • Part (e): Frequency of output waveform:   fo=2fi=2×50 Hz=100 Hzf_o = 2 f_i = 2 \times 50\,\text{Hz} = 100\,\text{Hz}

Example 8: Center-Tapped and Bridge Practice Problems

  • Problem Statement A: A two-diode center-tapped full-wave rectifier uses silicon diodes (Vk=0.7 VV_k = 0.7\,\text{V}). The secondary winding provides an RMS voltage of 100 V100\,\text{V} across each half, supplying a load resistor RL=975 ΩR_L = 975\,\Omega. Find (i) Average current, (ii) Average output voltage, and (iii) Diode PIV rating.

    • Solution:

    • Peak voltage per half: Vm=2(100 V)=141.42 VV_m = \sqrt{2} (100\,\text{V}) = 141.42\,\text{V}.

    • Peak load voltage: VL,max=Vm−Vk=141.42 V−0.7 V=140.72 VV_{L,\text{max}} = V_m - V_k = 141.42\,\text{V} - 0.7\,\text{V} = 140.72\,\text{V}.

    • (i) Average load voltage: Vdc=2(VL,max)π=2(140.72 V)π=89.57 VV_{\text{dc}} = \frac{2(V_{L,\text{max}})}{\pi} = \frac{2(140.72\,\text{V})}{\pi} = 89.57\,\text{V}.

    • (ii) Average load current: Idc=VdcRL=89.57 V975 Ω=91.8 mAI_{\text{dc}} = \frac{V_{\text{dc}}}{R_L} = \frac{89.57\,\text{V}}{975\,\Omega} = 91.8\,\text{mA}.

    • (iii) PIV rating: PIV≥2Vm−Vk=2(141.42 V)−0.7 V=282.1 V\text{PIV} \ge 2V_m - V_k = 2(141.42\,\text{V}) - 0.7\,\text{V} = 282.1\,\text{V}.

  • Problem Statement B: An ideal diode bridge rectifier is driven by a 220 Vrms220\,\text{V}_{\text{rms}}, 50 Hz50\,\text{Hz} AC mains through a transformer with a turns ratio of 4:14:1. The load resistance is RL=200 ΩR_L = 200\,\Omega. Determine VdcV_{\text{dc}}, IdcI_{\text{dc}}, and fof_o.

    • Solution:

    • Secondary RMS voltage: V2,rms=220 V4=55 VV_{2,\text{rms}} = \frac{220\,\text{V}}{4} = 55\,\text{V}.

    • Peak secondary voltage: Vm=2(55 V)=77.78 VV_m = \sqrt{2} (55\,\text{V}) = 77.78\,\text{V}.

    • Average DC voltage: Vdc=2Vmπ=2(77.78 V)π=49.6 VV_{\text{dc}} = \frac{2V_m}{\pi} = \frac{2(77.78\,\text{V})}{\pi} = 49.6\,\text{V}.

    • Average DC current: Idc=VdcRL=49.6 V200 Ω=248 mAI_{\text{dc}} = \frac{V_{\text{dc}}}{R_L} = \frac{49.6\,\text{V}}{200\,\Omega} = 248\,\text{mA}.

    • Output ripple frequency: fo=2fi=2×50 Hz=100 Hzf_o = 2 f_i = 2 \times 50\,\text{Hz} = 100\,\text{Hz}.

Shunt Capacitor Filter Circuits and Ripple Attenuation

Operating Mechanism

Center-tapped full-wave rectifier with shunt capacitor filter
  • A shunt capacitor filter consists of a high-value capacitor CC connected in parallel with the load resistor RLR_L.

  • Capacitive Reactance Behavior:   XC=12πfCX_C = \frac{1}{2\pi f C}

    • For high-frequency AC ripple components, XCX_C is small, shorting the ripple to ground.

    • For the zero-frequency DC component, XC→∞X_C \rightarrow \infty, forcing the steady direct current to flow through the load resistance RLR_L.

Capacitor charging and discharging waveforms showing ripple voltage
  • Charging Cycle (tct_c):

    • As the rectified input voltage rises from 0 V0\,\text{V} toward VmV_m, the diode is forward-biased, rapidly charging the capacitor up to VmV_m.

    • At the peak VmV_m, the capacitor voltage equals the input voltage, causing the diode to turn off because its anode and cathode are at the same potential.

  • Discharging Cycle (tdt_d):

    • As the input sinusoidal voltage drops below VmV_m, the diode remains reverse-biased ("off").

    • The capacitor supplies energy to the load, discharging exponentially with time constant τ=RLC\tau = R_L C.

    • For light loads (RLR_L large) or high capacitance CC, the discharge time constant is long compared to the period, causing the voltage to fall only slightly before the next rectified pulse turns the diode back on.

Ripple Factor and Voltage Expressions

  • Full-Wave Rectifier with Capacitor Filter:

    • Ripple factor expression:   γ=143fCRL\gamma = \frac{1}{4\sqrt{3} f C R_L}

    • Proportionality dependencies: γ∝1f\gamma \propto \frac{1}{f}, γ∝1C\gamma \propto \frac{1}{C}, γ∝1RL\gamma \propto \frac{1}{R_L}.

    • Because line frequency ff and load resistance RLR_L are determined by the application specifications, ripple reduction is achieved by selecting a sufficiently large capacitor CC.

    • RMS ripple voltage:   Vr(rms)=Idc43fCV_{r(\text{rms})} = \frac{I_{\text{dc}}}{4\sqrt{3} f C}

    • Average DC output voltage:   Vdc=Vm−Idc4fCV_{\text{dc}} = V_m - \frac{I_{\text{dc}}}{4 f C}

    • Expressed in terms of load voltage:   γ=Vr(rms)Vdc=Idc43fCVdc\gamma = \frac{V_{r(\text{rms})}}{V_{\text{dc}}} = \frac{I_{\text{dc}}}{4\sqrt{3} f C V_{\text{dc}}}

  • Half-Wave Rectifier with Capacitor Filter:

    • Because the capacitor must sustain the load over a full period TT rather than a half-period T/2T/2, the ripple voltage is doubled:   γ=123fCRL\gamma = \frac{1}{2\sqrt{3} f C R_L}   Vr(rms)=Idc23fCV_{r(\text{rms})} = \frac{I_{\text{dc}}}{2\sqrt{3} f C}   Vdc=Vm−Idc2fCV_{\text{dc}} = V_m - \frac{I_{\text{dc}}}{2 f C}

Capacitor Filter Performance: Worked Numerical Examples

Example 1: Full-Wave Filter Capacitor Sizing

  • Problem Statement: A full-wave rectifier with a capacitor filter supplies a load of 500 Ω500\,\Omega. The input frequency is 50 Hz50\,\text{Hz}.

    • (a) Calculate the capacitance required to maintain a ripple factor γ≤10%\gamma \le 10\%.

    • (b) Determine the resulting ripple factor if a 500 μF500\,\mu\text{F} capacitor is installed.

  • Solution:

    • Part (a): Given γ=0.1\gamma = 0.1, RL=500 ΩR_L = 500\,\Omega, f=50 Hzf = 50\,\text{Hz}:   C=143fγRL=143×50×0.1×500=117320.5=57.73 μFC = \frac{1}{4\sqrt{3} f \gamma R_L} = \frac{1}{4\sqrt{3} \times 50 \times 0.1 \times 500} = \frac{1}{17320.5} = 57.73\,\mu\text{F}

    • Part (b): With C=500 μFC = 500\,\mu\text{F}:   γ=143fCRL=143×50×(500×10−6)×500=186602.54=0.0115  (1.15%)\gamma = \frac{1}{4\sqrt{3} f C R_L} = \frac{1}{4\sqrt{3} \times 50 \times (500 \times 10^{-6}) \times 500} = \frac{1}{86602.54} = 0.0115\; (1.15\%)

Example 2: Strict Ripple Requirement Design

  • Problem Statement: A full-wave rectifier with a capacitor filter outputs a DC voltage of 10 V10\,\text{V} at a load current of 10 mA10\,\text{mA}. Assuming an AC supply frequency of 50 Hz50\,\text{Hz}, calculate the capacitance required to achieve a ripple factor γ≤0.001\gamma \le 0.001.

  • Solution:

    • Load resistance:   RL=VdcIdc=10 V10 mA=1 kΩR_L = \frac{V_{\text{dc}}}{I_{\text{dc}}} = \frac{10\,\text{V}}{10\,\text{mA}} = 1\,\text{k}\Omega

    • Capacitance required:   C=143fγRL=143×50×0.001×1000=10.34641=2886.75 μF≈2886 μFC = \frac{1}{4\sqrt{3} f \gamma R_L} = \frac{1}{4\sqrt{3} \times 50 \times 0.001 \times 1000} = \frac{1}{0.34641} = 2886.75\,\mu\text{F} \approx 2886\,\mu\text{F}

Example 3: Filter Ripple Voltage and DC Output Analysis

  • Problem Statement: A full-wave rectifier employs a 100 μF100\,\mu\text{F} filter capacitor delivering 50 mA50\,\text{mA} to a load. The peak rectified input voltage is 30 V30\,\text{V} at 50 Hz50\,\text{Hz}. Determine the DC output voltage, RMS ripple voltage, and the ripple factor.

  • Solution:

    • DC output voltage:   Vdc=Vm−Idc4fC=30 V−50×10−3 A4×50 Hz×(100×10−6 F)=30 V−0.050.02 V=30 V−2.5 V=27.5 VV_{\text{dc}} = V_m - \frac{I_{\text{dc}}}{4 f C} = 30\,\text{V} - \frac{50 \times 10^{-3}\,\text{A}}{4 \times 50\,\text{Hz} \times (100 \times 10^{-6}\,\text{F})} = 30\,\text{V} - \frac{0.05}{0.02}\,\text{V} = 30\,\text{V} - 2.5\,\text{V} = 27.5\,\text{V}

    • RMS value of the AC ripple component:   Vr(rms)=Idc43fC=50×10−343×50×(100×10−6)=0.050.03464=1.44 V≈1.4 VV_{r(\text{rms})} = \frac{I_{\text{dc}}}{4\sqrt{3} f C} = \frac{50 \times 10^{-3}}{4\sqrt{3} \times 50 \times (100 \times 10^{-6})} = \frac{0.05}{0.03464} = 1.44\,\text{V} \approx 1.4\,\text{V}

    • Ripple factor:   γ=Vr(rms)Vdc=1.44 V27.5 V=0.052≈0.05  (5%)\gamma = \frac{V_{r(\text{rms})}}{V_{\text{dc}}} = \frac{1.44\,\text{V}}{27.5\,\text{V}} = 0.052 \approx 0.05\; (5\%)

Example 4: Half-Wave Filter Sizing

  • Problem Statement: A half-wave rectifier with a capacitor filter drives a resistive load of 500 Ω500\,\Omega. If the output ripple must not exceed 10%10\% from a 50 Hz50\,\text{Hz} source, calculate the required capacitance CC.

  • Solution:

    • Applying the half-wave filter ripple formula with γ=0.10\gamma = 0.10:   γ=123fCRL  ⟹  0.10=123×50×C×500\gamma = \frac{1}{2\sqrt{3} f C R_L} \implies 0.10 = \frac{1}{2\sqrt{3} \times 50 \times C \times 500}   C=123×50×0.10×500=18660.25=1.1547×10−4 F=0.115 mF=115.47 μFC = \frac{1}{2\sqrt{3} \times 50 \times 0.10 \times 500} = \frac{1}{8660.25} = 1.1547 \times 10^{-4}\,\text{F} = 0.115\,\text{mF} = 115.47\,\mu\text{F}

Example 5: Percentage Ripple Factor from Load Parameters

  • Problem Statement: A full-wave rectifier uses a 100 μF100\,\mu\text{F} capacitor supplying a 2.5 kΩ2.5\,\text{k}\Omega load from a 50 Hz50\,\text{Hz} line. Determine the percentage ripple factor.

  • Solution:   γ=143fCRL=143×50×(100×10−6)×(2.5×103)\gamma = \frac{1}{4\sqrt{3} f C R_L} = \frac{1}{4\sqrt{3} \times 50 \times (100 \times 10^{-6}) \times (2.5 \times 10^3)}   γ=143×50×0.25=186.6025=0.011547=1.154%\gamma = \frac{1}{4\sqrt{3} \times 50 \times 0.25} = \frac{1}{86.6025} = 0.011547 = 1.154\%

Example 6: Peak Input Determination from Load Current and Ripple

  • Problem Statement: A full-wave rectifier with a 500 μF500\,\mu\text{F} filter capacitor delivers a load current of 200 mA200\,\text{mA} with an 8%8\% ripple factor at 50 Hz50\,\text{Hz}. Calculate the DC output voltage and the peak rectified voltage VmV_m.

  • Solution:

    • Expressing ripple factor in terms of load current and DC voltage:   γ=Idc43fCVdc  ⟹  Vdc=Idc43fCγ\gamma = \frac{I_{\text{dc}}}{4\sqrt{3} f C V_{\text{dc}}} \implies V_{\text{dc}} = \frac{I_{\text{dc}}}{4\sqrt{3} f C \gamma}   Vdc=200×10−343×50×(500×10−6)×0.08=0.20.013856=14.43 VV_{\text{dc}} = \frac{200 \times 10^{-3}}{4\sqrt{3} \times 50 \times (500 \times 10^{-6}) \times 0.08} = \frac{0.2}{0.013856} = 14.43\,\text{V}

    • Peak rectified input voltage VmV_m:   Vm=Vdc+Idc4fC=14.43 V+200×10−34×50×(500×10−6)=14.43 V+2 V=16.43 VV_m = V_{\text{dc}} + \frac{I_{\text{dc}}}{4 f C} = 14.43\,\text{V} + \frac{200 \times 10^{-3}}{4 \times 50 \times (500 \times 10^{-6})} = 14.43\,\text{V} + 2\,\text{V} = 16.43\,\text{V}

  • Problem Statement: A full-wave rectifier with a 500 μF500\,\mu\text{F} filter capacitor delivers a load current of 200 mA200\,\text{mA} with an 8%8\% ripple factor at 50 Hz50\,\text{Hz}. Calculate the DC output voltage and the peak rectified voltage VmV_m.

  • Solution:

    • Expressing ripple factor in terms of load current and DC voltage:   \gamma=\frac{I_{\text{dc}}}{4\sqrt{3} f C V_{\text{dc}}}\implies V_{\text{dc}}=\frac{I_{\text{dc}}}{4\sqrt{3} f C \gamma}=\frac{vrrms}{   V_{\text{dc}} = \frac{200 \times 10^{-3}}{4\sqrt{3} \times 50 \times (500 \times 10^{-6}) \times 0.08} = \frac{0.2}{0.013856} = 14.43\,\text{V}</p></li><li><p>Peakrectifiedinputvoltage</p></li><li><p>Peak rectified input voltageV_m:  :   V_m = V_{\text{dc}} + \frac{I_{\text{dc}}}{4 f C} = 14.43\,\text{V} + \frac{200 \times 10^{-3}}{4 \times 50 \times (500 \times 10^{-6})} = 14.43\,\text{V} + 2\,\text{V} = 16.43\,\text{V}</p></li></ul></li></ul><ul><li><p>ProblemStatement:Afull−waverectifierwitha</p></li></ul></li></ul><ul><li><p>Problem Statement: A full-wave rectifier with a500\,\mu\text{F}filtercapacitordeliversaloadcurrentoffilter capacitor delivers a load current of200\,\text{mA}withanwith an8\%ripplefactoratripple factor at50\,\text{Hz}.CalculatetheDCoutputvoltageandthepeakrectifiedvoltage. Calculate the DC output voltage and the peak rectified voltageV_m.</p></li><li><p>Solution:</p><ul><li><p>ExpressingripplefactorintermsofloadcurrentandDCvoltage:  .</p></li><li><p>Solution:</p><ul><li><p>Expressing ripple factor in terms of load current and DC voltage:   \gamma=\frac{I_{\text{dc}}}{4\sqrt{3} f C V_{\text{dc}}}\implies V_{\text{dc}}=\frac{I_{\text{dc}}}{4\sqrt{3} f C \gamma}=\frac{vrrms}{  Vdc=200×10−343×50×(500×10−6)×0.08=0.20.013856=14.43 VV_{\text{dc}} = \frac{200 \times 10^{-3}}{4\sqrt{3} \times 50 \times (500 \times 10^{-6}) \times 0.08} = \frac{0.2}{0.013856} = 14.43\,\text{V}

    • Peak rectified input voltage VmV_m:   Vm=Vdc+Idc4fC=14.43 V+200×10−34×50×(500×10−6)=14.43 V+2 V=16.43 VV_m = V_{\text{dc}} + \frac{I_{\text{dc}}}{4 f C} = 14.43\,\text{V} + \frac{200 \times 10^{-3}}{4 \times 50 \times (500 \times 10^{-6})} = 14.43\,\text{V} + 2\,\text{V} = 16.43\,\text{V}

Physics and Operational Characteristics of Zener Diodes

Physical Structure and Mechanism

Zener diode physical appearance and schematic symbol
  • A Zener diode is a silicon PN-junction device manufactured with heavy doping concentrations on both the P-type and N-type sides.

Heavily doped PN junction depletion region in a Zener diode
  • Heavy doping causes the depletion region width to be narrow (on the order of fractions of a micrometer).

  • When a reverse-bias voltage is applied, a high electric field develops across the narrow junction (≈3×105 V/cm\approx 3 \times 10^5\,\text{V/cm}).

  • Zener Breakdown Mechanism: The intense electric field exerts force on the bound valence electrons, tearing them directly from their covalent bonds. This creates a large concentration of electron-hole pairs, producing a sharp surge in reverse current at a specific breakdown voltage (VZV_Z) without destroying the device, provided the external circuit limits the current below rated limits.

Current-Voltage (I-V) Characteristics

Complete current-voltage characteristic curve of a Zener diode
  • Forward Bias (VF>0V_F > 0): Operates identically to a conventional PN junction diode, conducting heavily once the cut-in voltage (Vk≈0.7 VV_k \approx 0.7\,\text{V} for silicon) is reached.

  • Reverse Bias Pre-Breakdown (0<VR<VZ0 < V_R < V_Z): Only a small reverse saturation leakage current (Io≈10 μAI_o \approx 10\,\mu\text{A}) flows through the junction.

  • Reverse Breakdown Region (VR≥VZV_R \ge V_Z):

    • Once the reverse voltage reaches the breakdown threshold (VZV_Z), current increases sharply.

    • Operating limits: Current must remain between the minimum knee current (IZKI_{ZK} or IZ,minI_{Z,\text{min}}) and the maximum thermal rated current (IZMI_{ZM} or IZ,maxI_{Z,\text{max}}).

    • Maximum power dissipation rating: PZM=VZIZMP_{ZM} = V_Z I_{ZM}.

Equivalent Circuit Representations

Equivalent circuit models of a Zener diode across operating regions
  • Forward Bias: Represented as an ideal battery of 0.7 V0.7\,\text{V} in series with dynamic forward resistance rZr_Z.

  • Reverse Bias (Pre-Breakdown): Represented as an open circuit (or high leakage resistance RR→∞R_R \rightarrow \infty).

  • Zener Breakdown Region (ON State): Represented by a DC battery VZV_Z opposing the reverse polarity in series with a small dynamic Zener impedance (rZ=ZZT=ΔVZΔIZr_Z = Z_{ZT} = \frac{\Delta V_Z}{\Delta I_Z}). For an ideal Zener diode, rZ=0 Ωr_Z = 0\,\Omega, clamping the terminal voltage strictly at VZV_Z.

Essential Criteria for Voltage Regulation

  • The diode must be placed in a reverse-bias orientation.

  • The open-circuit supply voltage across the Zener terminals must exceed VZV_Z.

  • The Zener current must satisfy the operational window:   IZ,min≤IZ≤IZ,maxI_{Z,\text{min}} \le I_Z \le I_{Z,\text{max}}

Zener Diode Voltage Regulation: Theory and Analysis Cases

Case 1: Fixed Input Voltage ViV_i and Fixed Load Resistance RLR_L

Zener voltage regulator circuit with fixed input voltage and fixed load resistor
  • Analytical Procedure:

    • Step 1: Remove the Zener diode from the network to evaluate the open-circuit Thevenin voltage VV appearing across its terminals:   V=VL=RLViR+RLV = V_L = \frac{R_L V_i}{R + R_L}

    • Step 2: Compare the resulting open-circuit voltage VV against the rated Zener breakdown voltage VZV_Z:

    • If V<VZV < V_Z: The diode is OFF (in the non-conducting reverse-leakage state). It is replaced by an open circuit.       VL=V=RLViR+RLV_L = V = \frac{R_L V_i}{R + R_L}       IZ=0 AI_Z = 0\,\text{A}       IR=IL=ViR+RLI_R = I_L = \frac{V_i}{R + R_L}       VR=Vi−VL=IRRV_R = V_i - V_L = I_R R       PZ=VZIZ=0 WP_Z = V_Z I_Z = 0\,\text{W}

    • If V≥VZV \ge V_Z: The diode is ON (operating in the Zener breakdown region). The voltage across the diode clamps at VZV_Z and does not reach VV.       VL=VZV_L = V_Z       VR=Vi−VZV_R = V_i - V_Z       IR=VRR=Vi−VZRI_R = \frac{V_R}{R} = \frac{V_i - V_Z}{R}       IL=VLRL=VZRLI_L = \frac{V_L}{R_L} = \frac{V_Z}{R_L}       IZ=IR−ILI_Z = I_R - I_L       PZ=VZIZ≤PZMP_Z = V_Z I_Z \le P_{ZM}

Case 2: Fixed Supply Voltage ViV_i and Variable Load Resistance RLR_L

Zener voltage regulator circuit with fixed input voltage and variable load resistor
  • The series resistor current is fixed because ViV_i and VZV_Z are constants:   IR=Vi−VZRI_R = \frac{V_i - V_Z}{R}

  • Applying Kirchhoff's Current Law (KCL) at the output node:   IL=IR−IZI_L = I_R - I_Z

  • Minimum Load Resistance (RL,minR_{L,\text{min}}) Condition:

    • Occurs when the load draws the maximum allowable current (IL,maxI_{L,\text{max}}), leaving the Zener diode at its minimum conduction threshold (IZ=IZ,minI_Z = I_{Z,\text{min}}).   IL,max=IR−IZ,minI_{L,\text{max}} = I_R - I_{Z,\text{min}}   RL,min=VZIL,maxR_{L,\text{min}} = \frac{V_Z}{I_{L,\text{max}}}

    • When assuming an ideal lower threshold of IZ,min=0 AI_{Z,\text{min}} = 0\,\text{A}, the expression simplifies to:   IL,max=IRI_{L,\text{max}} = I_R   RL,min=VZIR=VZRVi−VZR_{L,\text{min}} = \frac{V_Z}{I_R} = \frac{V_Z R}{V_i - V_Z}

  • Maximum Load Resistance (RL,maxR_{L,\text{max}}) Condition:

    • Occurs when the load draws minimum current (IL,minI_{L,\text{min}}), forcing maximum current through the Zener diode without exceeding its power dissipation limit (IZ=IZ,max=PZMVZI_Z = I_{Z,\text{max}} = \frac{P_{ZM}}{V_Z}.   IL,min=IR−IZ,maxI_{L,\text{min}} = I_R - I_{Z,\text{max}}   RL,max=VZIL,minR_{L,\text{max}} = \frac{V_Z}{I_{L,\text{min}}}

    • Operating range for regulation: RL,min≤RL≤RL,maxR_{L,\text{min}} \le R_L \le R_{L,\text{max}}.

Case 3: Fixed Load Resistance RLR_L and Variable Supply Voltage ViV_i

Zener voltage regulator circuit with variable input voltage and fixed load resistor
  • Because the load resistance RLR_L is fixed and regulation holds VL=VZV_L = V_Z, the load current is constant:   IL=VZRLI_L = \frac{V_Z}{R_L}

  • Current through the series resistor varies with the input voltage: IR=IZ+ILI_R = I_Z + I_L.

  • Minimum Input Voltage (Vi,minV_{i,\text{min}}) Condition:

    • Required to initiate and maintain Zener breakdown (IZ=IZ,minI_Z = I_{Z,\text{min}}).   IR,min=IZ,min+ILI_{R,\text{min}} = I_{Z,\text{min}} + I_L   Vi,min=VZ+IR,minRV_{i,\text{min}} = V_Z + I_{R,\text{min}} R

    • If IZ,min=0 AI_{Z,\text{min}} = 0\,\text{A} (ideal diode turn-on boundary):   IR,min=IL=VZRLI_{R,\text{min}} = I_L = \frac{V_Z}{R_L}   Vi,min=VZ+(VZRL)R=VZ(R+RL)RLV_{i,\text{min}} = V_Z + \left(\frac{V_Z}{R_L}\right) R = \frac{V_Z (R + R_L)}{R_L}

  • Maximum Input Voltage (Vi,maxV_{i,\text{max}}) Condition:

    • Limited by the maximum safe Zener current (IZ,max=PZMVZI_{Z,\text{max}} = \frac{P_{ZM}}{V_Z}.   IR,max=IZ,max+ILI_{R,\text{max}} = I_{Z,\text{max}} + I_L   Vi,max=VZ+IR,maxRV_{i,\text{max}} = V_Z + I_{R,\text{max}} R

    • Allowable input voltage range: Vi,min≤Vi≤Vi,maxV_{i,\text{min}} \le V_i \le V_{i,\text{max}}.

Case 4: Variable Supply Voltage ViV_i and Variable Load Current ILI_L

  • In a general regulator circuit, both line voltage (Vi,min≤Vi≤Vi,maxV_{i,\text{min}} \le V_i \le V_{i,\text{max}}) and load demand (IL,min≤IL≤IL,maxI_{L,\text{min}} \le I_L \le I_{L,\text{max}}) fluctuate simultaneously.

  • Condition for Maximum Series Resistance (RmaxR_{\text{max}}) to Maintain Breakdown:

    • The Zener diode is most vulnerable to dropping out of regulation (IZ<IZ,minI_Z < I_{Z,\text{min}}) when the input voltage is at its lowest (Vi=Vi,minV_i = V_{i,\text{min}}) and the load draws its highest current (IL=IL,maxI_L = I_{L,\text{max}}).

    • Applying KVL under this worst-case scenario:   Rmax=Vi,min−VZIZ,min+IL,maxR_{\text{max}} = \frac{V_{i,\text{min}} - V_Z}{I_{Z,\text{min}} + I_{L,\text{max}}}

  • Condition for Minimum Series Resistance (RminR_{\text{min}}) to Prevent Thermal Overload:

    • The Zener diode is at risk of exceeding its maximum current rating (IZ>IZ,maxI_Z > I_{Z,\text{max}}) when the input voltage is at its highest (Vi=Vi,maxV_i = V_{i,\text{max}}) and the load draws its lowest current (IL=IL,minI_L = I_{L,\text{min}}).

    • Applying KVL under this complementary worst-case scenario:   Rmin=Vi,max−VZIZ,max+IL,minR_{\text{min}} = \frac{V_{i,\text{max}} - V_Z}{I_{Z,\text{max}} + I_{L,\text{min}}}

    • For successful voltage regulation over all operating conditions, the series resistor RR must satisfy:   Rmin≤R≤RmaxR_{\text{min}} \le R \le R_{\text{max}}

Zener Voltage Regulator Design: Worked Numerical Examples

Example 1: Evaluation of Fixed ViV_i and Fixed RLR_L

  • Problem Statement: A Zener regulator circuit has Vi=16 VV_i = 16\,\text{V}, series resistor R=1 kΩR = 1\,\text{k}\Omega, and a Zener diode rated at VZ=10 VV_Z = 10\,\text{V} with PZM=30 mWP_{ZM} = 30\,\text{mW}.

    • (a) Determine VLV_L, VRV_R, IZI_Z, and PZP_Z when RL=1.2 kΩR_L = 1.2\,\text{k}\Omega.

    • (b) Determine the same parameters when RL=3 kΩR_L = 3\,\text{k}\Omega.

  • Solution for Part (a) (RL=1.2 kΩR_L = 1.2\,\text{k}\Omega):

    • Step 1: Remove the Zener diode and calculate the open-circuit voltage VV:   V=RLViR+RL=(1.2 kΩ)(16 V)1 kΩ+1.2 kΩ=19.22.2=8.73 VV = \frac{R_L V_i}{R + R_L} = \frac{(1.2\,\text{k}\Omega)(16\,\text{V})}{1\,\text{k}\Omega + 1.2\,\text{k}\Omega} = \frac{19.2}{2.2} = 8.73\,\text{V}

    • Step 2: Compare VV to VZV_Z:

    • Since V=8.73 V<VZ=10 VV = 8.73\,\text{V} < V_Z = 10\,\text{V}, the diode is OFF.

    • Operating parameters:   VL=V=8.73 VV_L = V = 8.73\,\text{V}   VR=Vi−VL=16 V−8.73 V=7.27 VV_R = V_i - V_L = 16\,\text{V} - 8.73\,\text{V} = 7.27\,\text{V}   IZ=0 AI_Z = 0\,\text{A}   PZ=VZIZ=(10 V)(0 A)=0 WP_Z = V_Z I_Z = (10\,\text{V})(0\,\text{A}) = 0\,\text{W}

  • Solution for Part (b) (RL=3 kΩR_L = 3\,\text{k}\Omega):

    • Step 1: Calculate the open-circuit voltage VV:   V=RLViR+RL=(3 kΩ)(16 V)1 kΩ+3 kΩ=484=12 VV = \frac{R_L V_i}{R + R_L} = \frac{(3\,\text{k}\Omega)(16\,\text{V})}{1\,\text{k}\Omega + 3\,\text{k}\Omega} = \frac{48}{4} = 12\,\text{V}

    • Step 2: Compare VV to VZV_Z:

    • Since V=12 V≥VZ=10 VV = 12\,\text{V} \ge V_Z = 10\,\text{V}, the diode is ON.

    • Operating parameters:   VL=VZ=10 VV_L = V_Z = 10\,\text{V}   VR=Vi−VL=16 V−10 V=6 VV_R = V_i - V_L = 16\,\text{V} - 10\,\text{V} = 6\,\text{V}   IL=VLRL=10 V3 kΩ=3.33 mAI_L = \frac{V_L}{R_L} = \frac{10\,\text{V}}{3\,\text{k}\Omega} = 3.33\,\text{mA}   IR=VRR=6 V1 kΩ=6 mAI_R = \frac{V_R}{R} = \frac{6\,\text{V}}{1\,\text{k}\Omega} = 6\,\text{mA}   IZ=IR−IL=6 mA−3.33 mA=2.67 mAI_Z = I_R - I_L = 6\,\text{mA} - 3.33\,\text{mA} = 2.67\,\text{mA}   PZ=VZIZ=(10 V)(2.67 mA)=26.7 mWP_Z = V_Z I_Z = (10\,\text{V})(2.67\,\text{mA}) = 26.7\,\text{mW}

    • Thermal check: PZ=26.7 mW<PZM=30 mWP_Z = 26.7\,\text{mW} < P_{ZM} = 30\,\text{mW}, so the diode operates safely.

Example 2: Load Sizing for Conduction State

  • Problem Statement: A regulator has Vi=20 VV_i = 20\,\text{V}, series resistor RS=220 ΩR_S = 220\,\Omega, VZ=10 VV_Z = 10\,\text{V}, and PZ,max=400 mWP_{Z,\text{max}} = 400\,\text{mW}. Calculate VLV_L, ILI_L, IZI_Z, and IRI_R for (a) RL=180 ΩR_L = 180\,\Omega and (b) RL=470 ΩR_L = 470\,\Omega.

  • Solution for Part (a) (RL=180 ΩR_L = 180\,\Omega):

    • Open-circuit test:   VL=(180 Ω)(20 V)180 Ω+220 Ω=3600400=9 VV_L = \frac{(180\,\Omega)(20\,\text{V})}{180\,\Omega + 220\,\Omega} = \frac{3600}{400} = 9\,\text{V}

    • Since VL=9 V<VZ=10 VV_L = 9\,\text{V} < V_Z = 10\,\text{V}, the diode is non-conducting (OFF).   IL=IR=20 V220 Ω+180 Ω=50 mAI_L = I_R = \frac{20\,\text{V}}{220\,\Omega + 180\,\Omega} = 50\,\text{mA}   IZ=0 mAI_Z = 0\,\text{mA}   VL=9 VV_L = 9\,\text{V}

  • Solution for Part (b) (RL=470 ΩR_L = 470\,\Omega):

    • Open-circuit test:   VL=(470 Ω)(20 V)470 Ω+220 Ω=9400690=13.62 VV_L = \frac{(470\,\Omega)(20\,\text{V})}{470\,\Omega + 220\,\Omega} = \frac{9400}{690} = 13.62\,\text{V}

    • Since 13.62 V≥10 V13.62\,\text{V} \ge 10\,\text{V}, the diode is ON, clamping the output.   VL=10 VV_L = 10\,\text{V}   IL=10 V470 Ω=21.28 mAI_L = \frac{10\,\text{V}}{470\,\Omega} = 21.28\,\text{mA}   IR=20 V−10 V220 Ω=10 V220 Ω=45.45 mAI_R = \frac{20\,\text{V} - 10\,\text{V}}{220\,\Omega} = \frac{10\,\text{V}}{220\,\Omega} = 45.45\,\text{mA}   IZ=IR−IL=45.45 mA−21.28 mA=24.17 mAI_Z = I_R - I_L = 45.45\,\text{mA} - 21.28\,\text{mA} = 24.17\,\text{mA}

Example 3: Variable Load Resistance Range

  • Problem Statement: A circuit has Vi=50 VV_i = 50\,\text{V}, series resistor R=1 kΩR = 1\,\text{k}\Omega, VZ=10 VV_Z = 10\,\text{V}, IZM=32 mAI_{ZM} = 32\,\text{mA}, and IZ,min=1 mAI_{Z,\text{min}} = 1\,\text{mA}.

    • (a) Determine the range of RLR_L and ILI_L that maintains regulation at VL=10 VV_L = 10\,\text{V}.

    • (b) Determine the maximum wattage rating of the diode.

  • Solution:

    • Series resistor current:   IR=Vi−VZR=50 V−10 V1 kΩ=40 mAI_R = \frac{V_i - V_Z}{R} = \frac{50\,\text{V} - 10\,\text{V}}{1\,\text{k}\Omega} = 40\,\text{mA}

    • Maximum load current and minimum load resistance:   IL,max=IR−IZ,min=40 mA−1 mA=39 mAI_{L,\text{max}} = I_R - I_{Z,\text{min}} = 40\,\text{mA} - 1\,\text{mA} = 39\,\text{mA}   RL,min=VZIL,max=10 V39 mA=256.41 ΩR_{L,\text{min}} = \frac{V_Z}{I_{L,\text{max}}} = \frac{10\,\text{V}}{39\,\text{mA}} = 256.41\,\Omega

    • Minimum load current and maximum load resistance:   IL,min=IR−IZM=40 mA−32 mA=8 mAI_{L,\text{min}} = I_R - I_{ZM} = 40\,\text{mA} - 32\,\text{mA} = 8\,\text{mA}   RL,max=VZIL,min=10 V8 mA=1.25 kΩR_{L,\text{max}} = \frac{V_Z}{I_{L,\text{min}}} = \frac{10\,\text{V}}{8\,\text{mA}} = 1.25\,\text{k}\Omega

    • Range for regulation: 256.41 Ω≤RL≤1.25 kΩ256.41\,\Omega \le R_L \le 1.25\,\text{k}\Omega, with 8 mA≤IL≤39 mA8\,\text{mA} \le I_L \le 39\,\text{mA}.

    • Maximum wattage rating of the diode:   PZ,max=VZIZM=(10 V)(32 mA)=320 mWP_{Z,\text{max}} = V_Z I_{ZM} = (10\,\text{V})(32\,\text{mA}) = 320\,\text{mW}

Example 4: Variable Input Voltage Limits

  • Problem Statement: A regulator has series resistor R=220 ΩR = 220\,\Omega, VZ=20 VV_Z = 20\,\text{V}, IZM=60 mAI_{ZM} = 60\,\text{mA}, IZ,min=2 mAI_{Z,\text{min}} = 2\,\text{mA}, and a fixed load RL=1.2 kΩR_L = 1.2\,\text{k}\Omega. Find the permissible range of input voltage ViV_i to sustain regulation.

  • Solution:

    • Fixed load current:   IL=VZRL=20 V1.2 kΩ=16.67 mAI_L = \frac{V_Z}{R_L} = \frac{20\,\text{V}}{1.2\,\text{k}\Omega} = 16.67\,\text{mA}

    • Minimum Input Voltage (Vi,minV_{i,\text{min}}):   IR,min=IZ,min+IL=2 mA+16.67 mA=18.67 mAI_{R,\text{min}} = I_{Z,\text{min}} + I_L = 2\,\text{mA} + 16.67\,\text{mA} = 18.67\,\text{mA}   Vi,min=VZ+IR,minR=20 V+(18.67 mA)(220 Ω)=20 V+4.107 V=24.107 VV_{i,\text{min}} = V_Z + I_{R,\text{min}} R = 20\,\text{V} + (18.67\,\text{mA})(220\,\Omega) = 20\,\text{V} + 4.107\,\text{V} = 24.107\,\text{V}

    • If evaluated at the ideal boundary where IZ,min=0 AI_{Z,\text{min}} = 0\,\text{A}:   Vi,min=VZ(R+RL)RL=20(220+1200)1200=23.67 VV_{i,\text{min}} = \frac{V_Z(R + R_L)}{R_L} = \frac{20(220 + 1200)}{1200} = 23.67\,\text{V}

    • Maximum Input Voltage (Vi,maxV_{i,\text{max}}):   IR,max=IZM+IL=60 mA+16.67 mA=76.67 mAI_{R,\text{max}} = I_{ZM} + I_L = 60\,\text{mA} + 16.67\,\text{mA} = 76.67\,\text{mA}   Vi,max=VZ+IR,maxR=20 V+(76.67 mA)(220 Ω)=20 V+16.867 V=36.867 V≈36.87 VV_{i,\text{max}} = V_Z + I_{R,\text{max}} R = 20\,\text{V} + (76.67\,\text{mA})(220\,\Omega) = 20\,\text{V} + 16.867\,\text{V} = 36.867\,\text{V} \approx 36.87\,\text{V}

    • Permissible input voltage range: 24.11 V≤Vi≤36.87 V24.11\,\text{V} \le V_i \le 36.87\,\text{V}.

Example 5: Complete Regulator Design under Simultaneous Variations

  • Problem Statement: Design a Zener voltage regulator that maintains an output of Vo=10 VV_o = 10\,\text{V} across a varying load. The input supply voltage fluctuates by 20 V±10%20\,\text{V} \pm 10\%, and the load current fluctuates by 30 mA±20%30\,\text{mA} \pm 20\%. The Zener diode parameters are IZ,min=2 mAI_{Z,\text{min}} = 2\,\text{mA} and PZ,max=0.5 WP_{Z,\text{max}} = 0.5\,\text{W}.

  • Solution:

    • Input Voltage Limits:

    • Vi,nom=20 VV_{i,\text{nom}} = 20\,\text{V}

    • Fluctuation: 10%10\% of 20 V=2 V20\,\text{V} = 2\,\text{V}

    • Vi,min=20 V−2 V=18 VV_{i,\text{min}} = 20\,\text{V} - 2\,\text{V} = 18\,\text{V}

    • Vi,max=20 V+2 V=22 VV_{i,\text{max}} = 20\,\text{V} + 2\,\text{V} = 22\,\text{V}

    • Load Current Limits:

    • IL,nom=30 mAI_{L,\text{nom}} = 30\,\text{mA}

    • Fluctuation: 20%20\% of 30 mA=6 mA30\,\text{mA} = 6\,\text{mA}

    • IL,min=30 mA−6 mA=24 mAI_{L,\text{min}} = 30\,\text{mA} - 6\,\text{mA} = 24\,\text{mA}

    • IL,max=30 mA+6 mA=36 mAI_{L,\text{max}} = 30\,\text{mA} + 6\,\text{mA} = 36\,\text{mA}

    • Maximum Zener Current:   IZ,max=PZ,maxVZ=0.5 W10 V=50 mAI_{Z,\text{max}} = \frac{P_{Z,\text{max}}}{V_Z} = \frac{0.5\,\text{W}}{10\,\text{V}} = 50\,\text{mA}

    • Calculation of Maximum Series Resistor (RmaxR_{\text{max}}):   Rmax=Vi,min−VZIZ,min+IL,max=18 V−10 V2 mA+36 mA=8 V38 mA=210.52 ΩR_{\text{max}} = \frac{V_{i,\text{min}} - V_Z}{I_{Z,\text{min}} + I_{L,\text{max}}} = \frac{18\,\text{V} - 10\,\text{V}}{2\,\text{mA} + 36\,\text{mA}} = \frac{8\,\text{V}}{38\,\text{mA}} = 210.52\,\Omega

    • Calculation of Minimum Series Resistor (RminR_{\text{min}}):   Rmin=Vi,max−VZIZ,max+IL,min=22 V−10 V50 mA+24 mA=12 V74 mA=162.16 ΩR_{\text{min}} = \frac{V_{i,\text{max}} - V_Z}{I_{Z,\text{max}} + I_{L,\text{min}}} = \frac{22\,\text{V} - 10\,\text{V}}{50\,\text{mA} + 24\,\text{mA}} = \frac{12\,\text{V}}{74\,\text{mA}} = 162.16\,\Omega

    • Design Selection:

    • To guarantee constant voltage regulation without thermal runaway or dropout, the series resistor RR must be selected within the window:   162.16 Ω≤R≤210.52 Ω162.16\,\Omega \le R \le 210.52\,\Omega