EENG3150 Digital Technologies - Lecture 2: Sequential Logic

Lecture 2: Sequential Logic

Recap

• SR latch

• Combinational circuits vs Sequential circuits

• Asynchronous circuits vs Synchronous circuits

• SR Latch (NOR-gate latch, NAND-gate latch)

D Latch

• Logic symbol and Circuit of D Latch

• Enable (EN) input controls when the latch updates

D Latch Circuit Analysis

Truth Table and Operation

• When Enable = 1, Q follows input D.

• When Enable = 0, the latch holds the previous state (memory).

D-Type Flip-Flop

• Function table

Propagation Delay

• There are always propagation delays through logic gates.

• Function invalid during delay.

Limitations of Asynchronous Circuits

• There is an unstable period following an input change.

• Outputs cannot be used during this period.

• If many logic gates/latches change at different times, it can be difficult to find a stable situation for the overall circuit.

Synchronous Operation

• Synchronous operation, using a clock (Clk), allows all memory elements to be updated at the same time.

• Clocks: edge operation

• rising-edge triggered (positive-edge triggered)

• falling-edge triggered (negative-edge triggered)

D-Type Flip-Flop

• Positive edge-triggered

• Negative edge-triggered

D-type Flip-Flop with Asynchronous Inputs

• Synchronous inputs: the control inputs affect the operation of the circuit only at the moment of an appropriate transition of the clock signal.

• Asynchronous inputs: they are not bound by the state of the clock.

• Asynchronous inputs also can be active high or active low.

• Asynchronous Preset (Pr) and Clear (Cl) inputs are used to force the flip-flop to a specific state regardless of the clock or D input.

• Note: the active-low inverting dot

Active High Preset & Clear

Active Low Preset & Clear

Summary

• D type latch (circuit, logic symbol, function table)

• Synchronous operation

• D-type flip-flop (logic symbol, function table)

• D-type flop-flop with asynchronous inputs (logic symbol,