DC Interconnects and Circuit Basics

Core concepts: electric quantities

Current (I): flow of charge through a conductor; unit is amperes. Charge per electron: q_e = -1.6 \times 10^{-19} \text{ C}. Electron flow is opposite to conventional current.
Charge and materials: insulators, conductors, and semiconductors. Doping controls semiconductor conductance.
Voltage (V): potential difference; work needed to move charge; unit volts. Ground reference: zero potential.
Signals: analogue (real-valued) vs digital (discrete values, e.g., binary 0/1). AC vs DC: DC is steady; AC varies periodically (e.g., 60 Hz in mains). Noise can affect both.
Power: P = V I. Heat in circuits arises from power dissipation.
Interconnects in ICs: wires connect transistors; increasingly many metal layers as nodes shrink; cross-section and layer geometry affect resistance.

Ohm's law: V = I R. For a conductor with resistance R and voltage V, current is I = \dfrac{V}{R}.
Power relation (reiterated): P = V I.
Kirchhoff's laws:
- Kirchhoff's Voltage Law (KVL): the algebraic sum of voltages around a closed loop is zero.
- Kirchhoff's Current Law (KCL): the algebraic sum of currents into a circuit node is zero.
Ground and loops: circuits are analyzed using closed loops and node equations.

Equivalent resistance: R{eq} = \left( \dfrac{1}{R1} + \dfrac{1}{R_2} \right)^{-1}.
Same voltage across both: V1 = V2 = V. Currents: I1 = \dfrac{V}{R1}, \quad I2 = \dfrac{V}{R2}. Total current: I = I1 + I2.

R{eq} = R1 + R_2 = 9\;\Omega.
I = \dfrac{V}{R_{eq}} = \dfrac{12}{9} = \dfrac{4}{3} \text{ A} \approx 1.33 \text{ A}.
V1 = I R1 = \dfrac{4}{3} \times 3 = 4 \text{ V},\quad V2 = I R2 = \dfrac{4}{3} \times 6 = 8 \text{ V}.

IC wiring: multiple metal layers (example trend: up to 10–16 layers by advanced nodes) with copper interconnects; wires are orthogonal across layers (M1 runs north-south, M2 runs east-west, etc.).
Via connections: intermetal connections (VIA) connect adjacent layers to change direction.
Cross-section and resistance: wider cross-section lowers resistance; higher layers are wider/taller to compensate for longer distances and higher resistance.
Scaling effects: as feature sizes shrink, wires become narrower, increasing resistance; capacitance between close wires grows due to proximity (coupling between conductors).
Dielectrics and capacitance: insulating materials (dielectrics) with dielectric constant k affect inter-wire capacitance; low-k materials reduce capacitance; extreme cases (historical) used air gaps to reduce capacitance, but not common in practice.
Delay pathology: at deep submicron scales, interconnect delay becomes a dominant factor, often overwhelming gate delays if wires are long or densely packed.
Metal choices: aluminum historically used; copper common today; gold used in select high-speed/miniaturized contexts but costly.
Design insight: minimize interconnect length and optimize layout; sometimes parallelization/pipelining helps; alternative communication approaches (e.g., on-chip antennas) explored to reduce wire congestion.

Interconnects often dominate system delay; device speed improvements may be offset by wiring delays.
Shorter wires, smarter layouts, and reduced long-distance data movement are key for performance and energy efficiency.
When modeling circuits, include series/parallel resistance, stray capacitance, and potential via resistance.

Practical tool use: circuit solvers can verify series/parallel results for larger circuits; simulations yield node voltages and branch currents.
Real-world examples to think about: arranging multiple loads in series or parallel and predicting currents/voltages using the above laws.
Homework and resources: prompts and tutorials linked in course materials; encouragement to use reliable tools and document methods used.

Ohm's law: V = I R
Power: P = V I
Series: R{eq} = R1 + R2; V1 = I R1, \; V2 = I R_2
Parallel: R{eq} = \left( \dfrac{1}{R1} + \dfrac{1}{R2} \right)^{-1}; I1 = \dfrac{V}{R1}, \ I2 = \dfrac{V}{R2}, \ I = I1 + I_2
60 Hz: f = 60 \text{ Hz}