Sequential Logic

Introduction to Sequential Logic

  • Focus on arrangements of logic gates forming circuits.

  • Circuits process input signals to produce output signals.

  • Shift from combinatorial logic to sequential logic.

Hack ALU

  • Functionality of the ALU includes half adders, full adders, and 16-bit operations.

  • The operations are determined by control bits and can include addition, subtraction, and logical operations.

Circuit Behavior

  • Circuits may have feedback that causes propagation delays.

  • Critical to consider how long it takes for inputs to affect outputs (propagation delay).

SR Latch

  • Memorable characteristics: holds state when set or reset.

  • Issue arises when both inputs (R and S) are high; additional circuitry may be needed to handle this.

D Latch

  • Variation of an SR latch with data input (D) and clock (E).

  • Output reflects input when E is high, and holds last value when E is low.

Flip-Flops

  • Latches versus flip-flops: Flip-flops store input on clock transition (low to high).

  • Can incorporate a clear input for resetting.

  • Used in larger sequential circuits.

Clock Cycle

  • Master clock drives sequential circuits; each clock cycle synchronizes outputs.

  • Flip-flops update outputs on clock transitions, affecting circuit behavior.

Multiple Flip-Flops

  • To store multiple bits, use multiple flip-flops linked to a shared clock.

  • Each bit represented by a separate flip-flop, allowing grouped updates.

Registers

  • Circuits designed to control when the output updates while remaining in sync with the clock.

  • A 1-bit register uses a MUX to select inputs based on the load signal.

DFF Context

  • D flip-flops delay inputs by a clock cycle: output at time t reflects input from t-1.

  • This ensures stability and allows for input settling before updates occur.