Study Notes: MOS Field-Effect Transistors (MOSFETs)

Introduction to Three-Terminal Devices and MOSFETs

Three-Terminal Devices vs. Two-Terminal Devices: While the junction diode is the most basic two-terminal device, three-terminal devices are significantly more useful. They allow for signal amplification, digital logic, and memory applications.
Control Principle: The fundamental principle involves using the voltage between two terminals to control the current flowing through a third terminal. This enables the realization of a controlled source, forming the basis for amplifier design.
Switching Operation: In the extreme case, control signals can change current from zero to a large value, allowing the device to act as a switch, which is the basic element of a logic inverter in digital circuits.
Major Types: There are two primary types of three-terminal semiconductor devices: the Metal-Oxide-Semiconductor Field-Effect Transistor ( $\text{MOSFET}$ ) and the Bipolar Junction Transistor ( $\text{BJT}$ ).
Dominance of the MOSFET: The $\text{MOSFET}$ is the most widely used electronic device, particularly in Integrated Circuits ( $\text{ICs}$ ). Advantages include: - Small size (requiring minimal area on a silicon chip). - Relatively simple manufacturing process. - Low power consumption. - Capability to implement digital and analog functions almost exclusively without resistors. - High density: Up to $4 \times 10^{9}$ ( $4 \text{ billion}$ ) $\text{MOSFETs}$ can be packed onto a single $\text{VLSI}$ (Very-Large-Scale-Integrated) chip.
Mixed-Signal Design: This involves the implementation of both analog (amplifiers, filters) and digital functions on the same $IC$ chip.

Historical Development of Field-Effect Devices

1925: Julius E. Lilienfeld (University of Leipzig, Germany) filed a patent in Canada for a solid-state electric-field-controlled conductor.
1934: Oskar Heil (University of Cambridge, U.K.) filed a patent on a similar field-effect idea. Early concepts languished due to lack of suitable technology.
1947: Invention of the bipolar transistor at Bell Telephone Laboratories delayed field-effect development.
1952: William Shockley described the field-effect device in a paper.
1960: Dawon Kahng and Martin Atalla (Bell Labs) filed a patent on the insulated-gate field-effect device ( $\text{MOSFET}$ ).

Physical Structure of the n-Channel Enhancement-Type MOSFET

Substrate (Body): The device is fabricated on a single-crystal silicon wafer, typically a $p \text{-type}$ substrate ( $B$ ).
n+ Regions: Two heavily doped $n \text{-type}$ regions are created in the substrate, acting as the Source ( $S$ ) and the Drain ( $D$ ). The notation $n^{+}$ signifies heavy doping.
Insulator: A thin layer of silicon dioxide ( $SiO_2$ ) with thickness $t_{ox}$ (typically $1 \text{ nm}$ to $10 \text{ nm}$ ) is grown on the surface between the source and drain. Note: $1 \text{ nm} = 10^{-9} \text{ m}$ , $1 \, \mu\text{m} = 10^{-6} \text{ m}$ , and $1 \, \text{\AA} = 10^{-1} \text{ nm}$ .
Gate Electrode: Metal (or more commonly polysilicon) is deposited on top of the oxide layer to form the Gate ( $G$ ). This forms the Metal-Oxide-Semiconductor structure.
Terminals: There are four terminals: Gate ( $G$ ), Source ( $S$ ), Drain ( $D$ ), and Body/Substrate ( $B$ ).
Insulated Gate FET (IGFET): Also known as $\text{IGFET}$ because the gate is electrically insulated from the body by the oxide layer, resulting in extremely small gate current (order of $10^{-15} \text{ A}$ ).
Symmetry: The $\text{MOSFET}$ is a symmetrical device; source and drain can often be interchanged without changing characteristics.
Dimensions: Key parameters include Channel Length ( $L$ ) and Channel Width ( $W$ ). Typical ranges are $L = 0.03 \, \mu\text{m}$ to $1 \, \mu\text{m}$ and $W = 0.05 \, \mu\text{m}$ to $100 \, \mu\text{m}$ .

Physical Operation and Channel Formation

Zero Gate Voltage: With $v_{GS} = 0$ , two back-to-back $pn$ junctions exist between drain and source (drain-substrate and substrate-source). These junctions prevent current flow, creating a high resistance of approximately $10^{12} \, \Omega$ .
Applying vGS: When a positive voltage is applied to the gate: - Holes (majority carriers in $p \text{-type}$ substrate) are repelled from the region under the gate, creating a depletion region of negative bound charge. - Electrons are attracted from the $n^{+}$ source and drain regions into the channel region.
Inversion Layer: When enough electrons accumulate, an $n \text{-type}$ region is created connecting source and drain. This is called an inversion layer because the surface changes from $p \text{-type}$ to $n \text{-type}$ .
Threshold Voltage (Vt): The value of $v_{GS}$ at which a sufficient number of mobile electrons accumulate to form a conducting channel. Typically ranges from $0.3 \text{ V}$ to $1.0 \text{ V}$ .
Field Effect: The gate and channel form a parallel-plate capacitor with $SiO_2$ as the dielectric. The vertical electric field controls the amount of charge in the channel, hence the name \"Field-Effect Transistor.\"
Overdrive Voltage (vOV): The excess of gate-to-source voltage over the threshold voltage. - $v_{OV} \equiv v_{GS} - V_t$
Channel Charge (Q): The magnitude of the electron charge in the channel is given by: - $|Q| = C_{ox} (WL) v_{OV}$
Oxide Capacitance (Cox): Capacitance per unit gate area ( $\text{F/m}^2$ ): - $C_{ox} = \frac{\epsilon_{ox}}{t_{ox}}$ - $\epsilon_{ox} = 3.9 \epsilon_0 = 3.45 \times 10^{-11} \text{ F/m}$

The MOSFET as a Voltage-Controlled Resistance (Small vDS)

Conditions: v_{GS} > V_t and small $v_{DS}$ (e.g., $50 \text{ mV}$ ).
Channel Conductance (gDS): Because $v_{DS}$ is small, the voltage along the channel is uniform. The conductance is: - $g_{DS} = (\mu_n C_{ox}) (\frac{W}{L}) v_{OV}$
Process Transconductance Parameter (k'n): Determined by technology: - $k'n = \mu_n C{ox}$ (units: $\text{A/V}^2$ )
MOSFET Transconductance Parameter (kn): - $k_n = k'_n (\frac{W}{L})$
Drain Current (iD): - $i_D = [(\mu_n C_{ox}) (\frac{W}{L}) (v_{GS} - V_t)] v_{DS}$
Drain-to-Source Resistance (rDS): - $r_{DS} = \frac{1}{g_{DS}} = \frac{1}{(k'n) (\frac{W}{L}) v{OV}}$

Current-Voltage Characteristics as vDS Increases (Triode Region)

Channel Tapering: As $v_{DS}$ increases, the voltage between gate and channel decreases from $v_{GS}$ at the source end to $v_{GD} = v_{GS} - v_{DS}$ at the drain end. This causes the channel to become shallower at the drain end.
iD-vDS Equation (Triode Region): This applies when v_{DS} < v_{OV}. - $i_D = k'n (\frac{W}{L}) [(v{GS} - V_t) v_{DS} - \frac{1}{2} v_{DS}^2]$
Average Voltage: The factor $(v_{GS} - V_t - \frac{1}{2} v_{DS})$ represents the effective voltage averaged along the channel length.

Operation in the Saturation Region (vDS >= vOV)

Channel Pinch-Off: When $v_{DS} = v_{OV}$ , the gate-to-drain voltage $v_{GD} = V_t$ . The channel depth at the drain end becomes zero. Current continues to flow as electrons are swept across the depletion region.
Saturation Current: For $v_{DS} \ge v_{OV}$ , the current remains constant (saturates) at the value reached when $v_{DS} = v_{OV}$ . - $i_D = \frac{1}{2} k'n (\frac{W}{L}) (v{GS} - V_t)^2$
Saturation Voltage (VDSsat): - $V_{DSsat} = v_{OV} = v_{GS} - V_t$
Voltage-Controlled Current Source: In saturation, the $\text{MOSFET}$ behaves as a current source controlled by $v_{GS}$ . This region is used for amplification.

Large-Signal Equivalent Circuit Models and Output Resistance

Finite Output Resistance: In reality, increasing $v_{DS}$ beyond pinch-off slightly reduces the effective channel length ( $L \rightarrow L - \Delta L$ ), a phenomenon known as Channel-Length Modulation.
Channel-Length Modulation Parameter (\lambda): Current becomes dependent on $v_{DS}$ : - $i_D = \frac{1}{2} k'n (\frac{W}{L}) (v{GS} - V_{tn})^2 (1 + \lambda v_{DS})$
Early Voltage (VA): - $V_A = \frac{1}{\lambda} = V'_A L$ - $V'_A$ is process-dependent ( $5 \text{ V/}\mu\text{m}$ to $50 \text{ V/}\mu\text{m}$ ).
Output Resistance (ro): - $r_o = \frac{V_A}{I_D} = \frac{1}{\lambda I_D}$

The p-Channel Enhancement-Type MOSFET (PMOS)

Structure: Fabricated on an $n \text{-type}$ substrate with heavily doped $p^{+}$ source and drain regions.
Operation: Current is carried by holes. To turn the device on, $v_{GS}$ must be negative ( $v_{GS} \le V_{tp}$ or $|v_{GS}| \ge |V_{tp}|$ ).
Parameters: - $k'p = \mu_p C{ox}$ - Hole mobility $\mu_p$ is typically $0.25 \mu_n$ to $0.5 \mu_n$ , making $\text{PMOS}$ slower/weaker than $\text{NMOS}$ for the same size.
Saturation Condition (PMOS): - $v_{SD} \ge v_{SG} - |V_{tp}|$ - $i_D = \frac{1}{2} k'p (\frac{W}{L}) (v{SG} - |V_{tp}|)^2 (1 + |\lambda| v_{SD})$

Complementary MOS (CMOS) Technology

Definition: Utilizes both $\text{NMOS}$ and $\text{PMOS}$ transistors on a single silicon chip.
Fabrication: Typically, one transistor type (e.g., $\text{NMOS}$ ) is built in the substrate, while the other ( $\text{PMOS}$ ) is built in a created well of the opposite doping type (e.g., $n \text{-well}$ ).
Isolation: Thick silicon dioxide ( $SiO_2$ ) regions isolate the devices.
Application: dominant technology for both digital and analog circuits due to design flexibility and power efficiency.

Analysis of MOSFET Circuits at DC

Procedure: 1. Determine if the $\text{MOSFET}$ is conducting (|v_{GS}| > |V_t|). 2. If the mode is unknown, assume Saturation. 3. Solve the circuit equations using the saturation current formula. 4. Verify the condition $v_{DS} \ge v_{GS} - V_t$ . 5. If the condition fails (v_{DS} < v_{GS} - V_t), re-solve using the Triode equation.
Diode-Connected Transistor: Formed by connecting Gate to Drain ( $v_{GS} = v_{DS}$ ). Since v_{DS} > v_{GS} - V_t is always satisfied (for positive $V_t$ ), the device is always in saturation or cutoff. - $i = \frac{1}{2} k_n (v - V_t)^2$

Secondary Effects: Body Effect, Temperature, and Breakdown

Body Effect: When the Source is not connected to the Body ( $v_{SB} \ne 0$ ), the threshold voltage shifts. - $V_t = V_{t0} + \gamma [\sqrt{2\phi_f + V_{SB}} - \sqrt{2\phi_f}]$ - $V_{t0}$ : Threshold voltage at $v_{SB} = 0$ . - $\gamma$ : Body-effect parameter (typically $0.4 \text{ V}^{1/2}$ ). - $2\phi_f$ : Surface potential parameter (typically $0.6 \text{ V}$ ).
Temperature Effects: - $|V_t|$ decreases by about $2 \text{ mV/}^{\circ}\text{C}$ . - $\mu_n, \mu_p$ (and thus $k'$ ) decrease with temperature. - The net result of temperature increase is usually a decrease in drain current.
Breakdown Types: - Weak Avalanche: $pn$ junction breakdown at drain (typically $20 \text{ V}$ to $150 \text{ V}$ ). - Punch-through: Depletion region from drain reaches the source in short-channel devices ( $\sim 20 \text{ V}$ ). - Gate Oxide Breakdown: Occurs if v_{GS} > 30 \text{ V}; results in permanent damage. Protection is achieved via clamping diodes.
Velocity Saturation: In very short channel devices (L < 0.25 \, \mu\text{m}), drift velocity reaches a limit ( $\sim 10^7 \text{ cm/s}$ ). Current becomes linearly dependent on $v_{GS}$ rather than square-law.
Subthreshold Region: For $v_{GS}$ slightly below $V_t$ , small current flows with an exponential relationship to $v_{GS}$ . Used in specific low-power applications.

The Depletion-Type MOSFET

Structure: Has a physically implanted channel. Conducts even when $v_{GS} = 0$ .
Threshold Voltage: For an $n \text{-channel}$ depletion device, $V_{tn}$ is negative.
Modes of Operation: - Depletion Mode: Apply negative $v_{GS}$ to repel electrons and reduce channel conductivity. - Enhancement Mode: Apply positive $v_{GS}$ to attract more electrons and increase conductivity.
Circuit Symbol: Includes a shaded area next to the channel line to indicate the existing channel.