Sequential Logic Design Methodology and Applications
Academic Overview of Digital Design Lab #6: Sequential Design
The Digital Design Lab #6, part of the ECOM 1101 course at the Islamic University of Gaza Faculty of Engineering, focuses on the principles and practical applications of Sequential Logic Circuits. Under the guidance of Eng. Hashem M. Hejazy and Eng. Rania R. Alsayed for the Spring 2025/2026 term, students explore the methodologies required to design sequential systems that satisfy technical specifications while minimizing architectural costs.
Fundamental Methodology for Sequential Logic Circuit Design
Designing sequential logic circuits requires a structured approach to ensure the highest possible performance specifications and the lowest economic cost. The process follows three primary sequential steps. First, the designer must construct a state table. This table must strictly order the system inputs, the present state, the next state, and any resulting output if applicable. Once the table is established, it must be reduced by systematically identifying and eliminating repeated or redundant states. Second, the designer derives the functional logic expressions from the reduced state table. Finally, the physical logic circuit is drawn based on the resulting mathematical functions.
Example 1: Sequential Circuit Design with Dual D Flip-Flops
This example details the design of a sequential circuit using two D flip-flops, designated as and , and a single external input variable . The operational logic of the circuit is defined by the following conditions: if the input , the state of the circuit must remain unchanged (hold state); if the input , the circuit must cycle through a specific sequence of state transitions: , repeating this loop indefinitely as long as the input remains active.
The initial phase of the solution involves constructing the state table to determine the present state, the input, and the resulting next states for both flip-flops. The state table is as follows:
| Present State () | Present State () | Input () | Next State () | Next State () |
|---|---|---|---|---|
Following the state table construction, Karnaugh maps are utilized to find the logic functions for the next-state equations. For the flip-flop , the resulting function is determined to be . For the flip-flop , the function is derived as . The logical implementation involves a circuit where D flip-flop and D flip-flop receive these inputs, and their outputs feed back into the logic as the present states and .
Example 2: Traffic Light System with Pedestrian Crossing
The second design challenge involves a traffic light system that integrates vehicle signals with a pedestrian crossing mechanism. This system utilizes two D flip-flops for state management. The vehicular signals are Red (), Yellow (), and Green (). The pedestrian signals are defined as Red () and Green ().
The operational sequence for the signals is defined as: , which then repeats. Each symbolic state corresponds to specific signal outputs:
- State : Vehicle Red (), vehicle Yellow (), vehicle Green (), pedestrian Red (), pedestrian Green ().
- State : Vehicle Red (), vehicle Yellow (), vehicle Green (), pedestrian Red (), pedestrian Green ().
- State : Vehicle Red (), vehicle Yellow (), vehicle Green (), pedestrian Red (), pedestrian Green ().
- State : Vehicle Red (), vehicle Yellow (), vehicle Green (), pedestrian Red (), pedestrian Green ().
To facilitate the design, the state encoding for the two D flip-flops is as follows: State is encoded as , State as , State as , and State as .
The truth table for the traffic light system is organized as follows:
| Present State () | Next State () | Vehicle Red () | Vehicle Yellow () | Vehicle Green () | Pedestrian Red () | Pedestrian Green () |
|---|---|---|---|---|---|---|
Based on this truth table, the resulting logical functions for the flip-flops and outputs are derived:
Example 3: Vending Machine Controller Design
This application focuses on a controller for a vending machine that dispenses gum costing . The machine features a single slot accepting only nickels () and dimes (). A sensor provides inputs (for nickel) and (for dime). The controller includes a clock and a reset input and triggers a "release" signal once the total deposited amount is greater than or equal to .
Design observations for the vending machine include:
- The release signal is asserted when the total reaches at least .
- If a nickel is deposited, .
- If a dime is deposited, .
- When no coin is deposited, both and equal .
- The inputs and are mutually exclusive and can never both be simultaneously.
- The machine does not provide change or store credits.
The system utilizes four symbolic states corresponding to the money accumulated:
- :
- :
- :
- :
With four states, a minimum of two bits ( flip-flops) is required for encoding. In this design, D flip-flops (DFF) are used, where the next state is equal to the input at the arrival of the active clock edge. The derived logic equations for the vending machine controller are:
The physical implementation is shown through logic gates connecting input signals , , and flip-flop outputs to generate the next state inputs and , as well as the output . A Reset () line is also included for system initialization.
Homework: Intersection Traffic Light Control System
Students are assigned to design a traffic light control system for a specific intersection based on several constraints provided in an intersection diagram. The design must adhere to the following four conditions:
- The intersection is composed of four main roads, and each road consists of two directions: one incoming and one outgoing.
- Each direction is equipped with exactly one traffic light, which is designed exclusively for vehicles. The system does not include pedestrian signals.
- Turning maneuvers, whether left or right into adjacent roads, are strictly prohibited. Vehicles are only permitted to move straight ahead.
- To maximize efficiency, vehicles moving in directly opposite directions (such as Northbound and Southbound) are permitted to move simultaneously, as their logical paths do not intersect.