Sequential Logic Design Methodology and Applications

Academic Overview of Digital Design Lab #6: Sequential Design

The Digital Design Lab #6, part of the ECOM 1101 course at the Islamic University of Gaza Faculty of Engineering, focuses on the principles and practical applications of Sequential Logic Circuits. Under the guidance of Eng. Hashem M. Hejazy and Eng. Rania R. Alsayed for the Spring 2025/2026 term, students explore the methodologies required to design sequential systems that satisfy technical specifications while minimizing architectural costs.

Fundamental Methodology for Sequential Logic Circuit Design

Designing sequential logic circuits requires a structured approach to ensure the highest possible performance specifications and the lowest economic cost. The process follows three primary sequential steps. First, the designer must construct a state table. This table must strictly order the system inputs, the present state, the next state, and any resulting output if applicable. Once the table is established, it must be reduced by systematically identifying and eliminating repeated or redundant states. Second, the designer derives the functional logic expressions from the reduced state table. Finally, the physical logic circuit is drawn based on the resulting mathematical functions.

Example 1: Sequential Circuit Design with Dual D Flip-Flops

This example details the design of a sequential circuit using two D flip-flops, designated as AA and BB, and a single external input variable xinx_{in}. The operational logic of the circuit is defined by the following conditions: if the input xin=0x_{in} = 0, the state of the circuit must remain unchanged (hold state); if the input xin=1x_{in} = 1, the circuit must cycle through a specific sequence of state transitions: 00→01→11→10→0000 \rightarrow 01 \rightarrow 11 \rightarrow 10 \rightarrow 00, repeating this loop indefinitely as long as the input remains active.

The initial phase of the solution involves constructing the state table to determine the present state, the input, and the resulting next states for both flip-flops. The state table is as follows:

Present State (AA)Present State (BB)Input (XX)Next State (A(t+1)A(t+1))Next State (B(t+1)B(t+1))
0000000000
0000110011
0011000011
0011111111
1100001100
1100110000
1111001111
1111111100

Following the state table construction, Karnaugh maps are utilized to find the logic functions for the next-state equations. For the flip-flop AA, the resulting function is determined to be A(t+1)=A′x+BxA(t+1) = A'x + Bx. For the flip-flop BB, the function is derived as B(t+1)=A′x+Bx′B(t+1) = A'x + Bx'. The logical implementation involves a circuit where D flip-flop AA and D flip-flop BB receive these inputs, and their outputs QQ feed back into the logic as the present states AA and BB.

Example 2: Traffic Light System with Pedestrian Crossing

The second design challenge involves a traffic light system that integrates vehicle signals with a pedestrian crossing mechanism. This system utilizes two D flip-flops for state management. The vehicular signals are Red (RR), Yellow (YY), and Green (GG). The pedestrian signals are defined as Red (FF) and Green (TT).

The operational sequence for the signals is defined as: RT→RYF→GF→YF→RTRT \rightarrow RYF \rightarrow GF \rightarrow YF \rightarrow RT, which then repeats. Each symbolic state corresponds to specific signal outputs:

  • State RTRT: Vehicle Red (11), vehicle Yellow (00), vehicle Green (00), pedestrian Red (00), pedestrian Green (11).
  • State RYFRYF: Vehicle Red (11), vehicle Yellow (11), vehicle Green (00), pedestrian Red (11), pedestrian Green (00).
  • State GFGF: Vehicle Red (00), vehicle Yellow (00), vehicle Green (11), pedestrian Red (11), pedestrian Green (00).
  • State YFYF: Vehicle Red (00), vehicle Yellow (11), vehicle Green (00), pedestrian Red (11), pedestrian Green (00).

To facilitate the design, the state encoding for the two D flip-flops is as follows: State RTRT is encoded as Q1Q0=00Q_1Q_0 = 00, State RYFRYF as 0101, State GFGF as 1010, and State YFYF as 1111.

The truth table for the traffic light system is organized as follows:

Present State (Q1,Q0Q_1, Q_0)Next State (Q1+,Q0+Q_1+, Q_0+)Vehicle Red (RR)Vehicle Yellow (YY)Vehicle Green (GG)Pedestrian Red (FF)Pedestrian Green (TT)
0,00, 00,10, 11100000011
0,10, 11,01, 01111001100
1,01, 01,11, 10000111100
1,11, 10,00, 00011001100

Based on this truth table, the resulting logical functions for the flip-flops and outputs are derived: Q1+=Q1⊕Q0Q1+ = Q1 \oplus Q0Q1+=Q0′Q1+ = Q0'R=(Q1⊕Q0)′R = (Q1 \oplus Q0)'Y=Q0′Y = Q0'G=Q1′⋅Q0G = Q1' \cdot Q0Rh=(Q0+Q1)′Rh = (Q0 + Q1)'Gh=Q0Q1Gh = Q0 Q1

Example 3: Vending Machine Controller Design

This application focuses on a controller for a vending machine that dispenses gum costing 15 cents15\,\text{cents}. The machine features a single slot accepting only nickels (5 cents5\,\text{cents}) and dimes (10 cents10\,\text{cents}). A sensor provides inputs nn (for nickel) and dd (for dime). The controller includes a clock and a reset input and triggers a "release" signal once the total deposited amount is greater than or equal to 15 cents15\,\text{cents}.

Design observations for the vending machine include:

  • The release signal is asserted when the total reaches at least 15 cents15\,\text{cents}.
  • If a nickel is deposited, n=1n = 1.
  • If a dime is deposited, d=1d = 1.
  • When no coin is deposited, both nn and dd equal 00.
  • The inputs nn and dd are mutually exclusive and can never both be 11 simultaneously.
  • The machine does not provide change or store credits.

The system utilizes four symbolic states corresponding to the money accumulated:

  • S0S0: 0 cents0\,\text{cents}
  • S1S1: 5 cents5\,\text{cents}
  • S2S2: 10 cents10\,\text{cents}
  • S3S3: ≥15 cents\ge 15\,\text{cents}

With four states, a minimum of two bits (22 flip-flops) is required for encoding. In this design, D flip-flops (DFF) are used, where the next state Q(t+1)Q(t+1) is equal to the input D(t)D(t) at the arrival of the active clock edge. The derived logic equations for the vending machine controller are: D0=Q1Q0n+Q0n+Q1Q0dD0 = Q_1Q_0n + Q_0n + Q_1Q_0dD1=Q1Q0+Q1′Q0n+QjdD1 = Q_1Q_0 + Q'_1Q_0n + Q_jdrelease=Q1Q0\text{release} = Q_1Q_0

The physical implementation is shown through logic gates connecting input signals dd, nn, and flip-flop outputs to generate the next state inputs D1D1 and D0D0, as well as the output releaserelease. A Reset (RR) line is also included for system initialization.

Homework: Intersection Traffic Light Control System

Students are assigned to design a traffic light control system for a specific intersection based on several constraints provided in an intersection diagram. The design must adhere to the following four conditions:

  1. The intersection is composed of four main roads, and each road consists of two directions: one incoming and one outgoing.
  2. Each direction is equipped with exactly one traffic light, which is designed exclusively for vehicles. The system does not include pedestrian signals.
  3. Turning maneuvers, whether left or right into adjacent roads, are strictly prohibited. Vehicles are only permitted to move straight ahead.
  4. To maximize efficiency, vehicles moving in directly opposite directions (such as Northbound and Southbound) are permitted to move simultaneously, as their logical paths do not intersect.