All - Unit 1-2-3
Page 1: Introduction to Computer Architecture
Basic Structure of Computers
Functional Units
Basic Operational Concepts
Bus Structures
Software
Performance and Metrics
Multiprocessors and Multicomputer
Memory Locations and Addresses
Instructions and Instruction Sequencing
Addressing Modes
Fixed Point and Floating Point Representations
Page 2: Definition of a Computer
What is a Computer?
Origin: Comes from the word "COMPUTE" which means "TO CALCULATE".
Definition: An electronic device that does the following:
Accepts information
Processes data
Stores data
Produces output
Components: Two main parts:
Hardware
Software
Page 3: Understanding Software
What is Software?
Definition: A set of instructions directing the computer to perform specific operations.
Categories of Software:
Application Software
System Software
Developer Software
Examples of Software:
Business: Boot loaders, Compilers
Communication: Device drivers, Software development tools
Entertainment: Operating systems, Simulation
Page 4: Generations of Computer Languages
First-Generation Languages:
Also known as Machine Languages.
Consists of commands represented in binary (1s and 0s).
Second-Generation Languages:
Assembly Languages, uses abbreviated command words (opcodes) such as LDA for Load.
Third-Generation Languages:
Easier programming with commands like PRINT and INPUT (e.g., Basic, Pascal, Fortran).
Fourth-Generation Languages:
Developed around 1969, resemble human languages.
Fifth-Generation Languages:
Focus on Artificial Intelligence applications.
Page 5: Source Code Example
C++ Addition Program:
#include<iostream>
using namespace std;
int main() {
int n1, n2, sum;
n1 = 10;
n2 = 12;
sum = n1+n2;
cout << "Addition of n1 & n2: " << sum;
return 0;
}Processing Handling:
Preprocessor and Compiler translate C++ into Assembly code.
Page 6: Assembly Code Generation
Assembly Code Generation Process:
The assembler generates object code.
Linkers prepare executable modules and loaders execute by loading them into memory.
Example of Executable Code:
0010 0001 0000 0100...Page 7: Functional Units
Programs and Instructions:
A program consists of a list of instructions
Processor Functionality:
Fetches instructions from memory, processes them sequentially.
Information Encoding:
Encoded in bits (0 or 1)
Coding Schemes:
ASCII (American Standard Code for Information Interchange)
EBCDIC (Extended Binary Coded Decimal Interchange Code)
Page 8: Input Units and Memory
Input Units:
Input information to the computer (e.g., Keyboard, Mouse, Scanner, etc.).
Memory Types:
Primary Memory: RAM, ROM, Cache
Secondary Memory: Magnetic tape, Hard Disk, etc.
Memory Hierarchy:
Access time varies based on the memory type.
RAM Overview:
Fast access, stores running programs, significantly faster than hard drives.
Page 9: ALU and Control Unit
ALU - Arithmetic Logic Unit:
Handles arithmetic and logical operations.
Processor Operations:
Involves reading/writing data and includes registers for internal memory.
Control Unit:
Sends control signals to other units and coordinates their operations.
Page 10: Basic Operational Concepts
Processor Composition:
Comprises ALU, Control Circuits, and Registers.
Key Registers:
Instruction Register (IR), Program Counter (PC), Memory Address Register (MAR), Memory Data Register (MDR).
Page 11: Interrupt Signals
Interrupt Handling:
Programs may be interrupted for urgent servicing requests from I/O devices.
State restoration after service completion.
Page 12: Bus Structures
Definition of Bus:
Pathway of wires connecting devices.
Bus Operation Types:
Single Bus: Simple, low-cost, flexible.
Multi-bus: Multiple buses for concurrency and parallel operations.
Page 13: Software Functions
Role of System Software:
Manages user commands, application programs, file management, I/O control, etc.
Page 14: Timing Diagrams
Concept of Timing Diagrams:
Illustrates concurrent execution of applications by operating systems (multiprogramming).
Page 15: Performance Metrics
Performance Measures:
Speed of execution (elapsed time, processor time).
Performance Equation:
T = N x S / R
T = Execution Time, N = Dynamic Instruction Count, S = CPU cycle count, R = Clock rate.
Page 16: Improving Performance
Performance Factors:
T: Time needed for instruction execution should be minimized.R: Clock rate should be maximized (higher rate improves throughput).
Page 17: Techniques for Performance Improvement
Clock Rate Adjustments:
Enhancing integrated circuits and processing time to reduce
S(steps per instruction).
Instruction Set Types:
RISC and CISC examples.
Page 18: Performance Measurement
Evaluation Methods:
Use of standard benchmark programs and evaluation corporations (SPEC) for performance ratings.
Page 19: Multiprocessor and Multicomputer Systems
Definition:
Multiprocessor: Utilizes multiple CPUs within a computer.
Multicomputer: Group of interconnected computers for enhanced computational power.
Page 20: Memory Locations and Addresses
Memory Structure:
Millions of storage cells (bit, bytes, words).
Addressing:
Each memory location has a unique address for access.
Page 21: Memory Addressing Techniques
Addressing Requirements:
Unique numbering for memory access.
Address Space:
Defined by addr size (e.g., 24-bit generates 16,777,216 locations).
Page 22: Performance Comparison of Processors
Performance Analysis:
Three processors comparison based on clock rate and instructions per second.
Page 23: Address Assignment Techniques
Big-endian vs Little-endian:
Different methods of byte-order assignment in memory addresses.
Page 24: Performance Definition
Performance Formula:
Defined as 1/Execution time.
Page 25: Instruction Sequencing
Instruction Types:
Data Transfer
Arithmetic/Logic
Program Control
I/O Transfers
Page 26: Instruction Formats
Instruction Classification:
Three Address
Two Address
One Address
Zero Address
Page 27: Straight-Line Sequencing
PC Functionality:
PC holds the address of the next instruction; describes linear fetching execution.
Page 28: Branching Mechanism
Branch Instruction Handling:
Changes PC content to jump to specified addresses.
Page 29: Instruction Sequencing Example
Example Sequence:
Demonstrates the process of sequential instruction execution.
Page 30: Looping Instructions
Example of Looping:
Illustrates how loops can manage repeated operations in programs.
Page 31: Conditional Code Register
Purpose of the Conditional Code Register:
Tracks operation results and adjusts branches.
Page 32: Addressing Modes Overview
Operand Specification:
Various methods to specify the location of operands in instructions.
Page 33: Implementation of Variables and Constants
Addressing Modes:
Immediate Mode
Register Mode
Absolute Mode
Page 34: Indirect and Other Addressing Modes
More Addressing Techniques:
Indirect Mode
Index Mode
Page 35: Base with Index Addressing Modes
Advanced Addressing Methods:
Base with Index
Base with Index and Offset
Page 36: Relative and Autoincrement Modes
Further Addressing Approaches:
Relative Mode
Autoincrement Mode
Page 37: Autodecrement and Other Addressing Modes
Completing the Addressing Modes:
Autodecrement Mode
Page 38: Case Study on Addressing
Register Examples:
Analysis of effective addresses for several operations involving registers.
Page 39: Addressing Mode Identification
Assignment of Addressing Modes:
Different instructions analyzed to identify addressing techniques.
Page 40: Additional Register Operations
Further Analysis on Addressing Modes:
Identifying addressing modes in various examples.
Page 41: Register Operations Analysis
Effective Address Analysis:
Further detailed breakdown and calculation of effective addresses in operations.
Page 42: Floating Point Representation
IEEE 754 Floating-Point Standards:
Single and Double Precision details.
Page 43: Introduction to Basic Processing Unit
Fundamental Concepts Covered:
Execution of instructions detailing multiple bus organization and types of control.
Page 44: Single Bus Organization
Key Features:
Description of operations and components utilized within this architecture.
Page 45: Instruction Execution Overview
Execution Steps:
Register transfer, ALU operations, memory fetching, and storing.
Page 46: Detailed Instructions on Register Transfer
Steps for Operations:
Example of MOVE instruction and control signals supporting this process.
Page 47: Memory Fetch Instructions
Detailed Steps for Memory Operations:
How to store information effectively from and to memory addresses.
Page 48: Memory Write Operations
Steps for Storing Information:
How data is moved into memory locations through control signals.
Page 49: Execution of Complete Instruction
Detailed Example:
Steps illustrating execution of instruction from fetching to processing.
Page 50: Three Bus Organization
Architecture Overview:
Advantages over single bus systems leading to fewer cycles needed.
Page 51: Three Bus Architecture Details
Diagram of Three Bus Structure:
Components and functions of the three-bus organization.
Page 52: Example of BUS Organization in use
Instruction Execution Overview:
Steps visualizing ADD instruction operation with register outputs.
Page 53: Further Instruction Example within BUS Architecture
Instruction Execution Steps for ADD:
Detailed breakdown aligning with bus architecture execution.
Page 54: Conditional Branch Instruction Execution
Handling branch Instructions:
How conditional branch instructions impact pipeline flow.
Page 55: Hardware Design for Signed-magnitude Data
Overview of Sign-Magnitude Operations
Page 56: Hardwired Control Unit
Description of Control Process:
Steps utilized within a hardwired control unit for operation.
Page 57: Detailed Functionality of Hardwired Control Unit
Assumptions and Operation Cycle Management:
Control sequences initiated through clock signals.
Page 58: Control Unit Signal Generation
Operation of Control Unit Signal Generation:
Design aspects influencing control signal logistics.
Page 59: Generating Control Signals for Instructions
Steps for Instruction Control Signal Creation:
Process overview of various instructions within control execution.
Page 60: Branch Management Techniques
Managing PC for Branch Instructions:
Detailed signal management overview for effective branching.
Page 61: Microprogrammed Control Unit Overview
Functionality and Execution in Microprogrammed Systems:
Control signal generation methodology within microprogrammed units.
Page 62: Microprogrammed Control Signals
Description of Control Words in Microprogrammed Units:
Significance of microinstructions and control routines.
Page 63: Control Signals Mechanism in Microprogramming
Sequential Reading of Control Words:
Process and significance of the control memory in operations.
Page 64: Horizontal Micro-instruction Encoding
Advantages and Disadvantages Explained:
Trade-offs of parallel activation vs. memory size.
Page 65: Vertical Micro-instruction Encoding
Control Signals Representation:
Efficient management of control signal allocation.
Page 66: Hardwired vs Microprogrammed Control Units
Comparison of Control Units:
Differences in architecture, speed, and modification flexibility.
Page 67: Microprogrammed Control Details
Functionality Deconstruction into Microprograms:
Overview on microroutines and the mechanics behind microprogrammed control.
Page 68: Control Stores and Signals Management
Understanding Control Signals Structure:
Format and function of the key control mass storage.
Page 69: Introduction to Pipelining
Basic Concepts and Overview:
Introduction to pipelining as it relates to performance acceleration.
Page 70: Pipelining Fundamentals
Explanation of Concurrent Execution Strategies:
Techniques that enhance processor throughput.
Page 71: Two-stage Pipeline Representation
Overview of Operation within two stages of pipelining.
Page 72: Four-stage Pipeline Representation
Full pipeline discussions including memory access solutions.
Page 73: Pipeline Completion and Hazards
Description of Instruction Flow and Stalls:
Exploration of stalls and their performance implications.
Page 74: Types of Hazards in Pipelining
Definition and Exploration of Different Hazard Types:
Key hazard categories affecting pipeline performance.
Page 75: Specific Instruction Hazards
Details on Instruction Hazards and Their Management:
Branch instruction delays and cache misses discussed.
Page 76: Structural Hazard Considerations
Description of Hardware Resource Conflicts:
Understanding how multiple instructions can conflict during execution.
Page 77: Minimizing Data Hazards
Strategies for Reducing Errors and Delays:
Identifying methods to improve data dependency issues.
Page 78: Resolving Data Hazards in Pipelined Operations
Explanation of Operand Handling When Data Dependent:
Techniques discussed for managing dependencies in executions.
Page 79: Techniques for Overcoming Data Hazards
Overview of Techniques:
Operand Forwarding
Software Handling
Page 80: Operand Forwarding Techniques
Techniques Impact on Data Dependency Management:
Explanation of immediate operand feedback into execution cycles.
Page 81: Handling Side Effects in Execution
Impact of dependencies through implicit flags:
Processing techniques that utilize register flags for operations.
Page 82: Instruction Hazards Management
Control Hazards and Their Effects:
Overview of how instruction delays can impact execution.
Page 83: Reducing Penalties of Branch Instructions
Explanation of Instruction Disruptions:
Techniques effective for reducing penalties in branch operations.
Page 84: Instruction Queue Management
Techniques for Prefetching Instructions:
Queue transaction systems designed to enhance flow control.
Page 85: Branching Control in Advanced Processors
Instruction Execution during Unexpected Conditions:
Management of operations during branch execution conflicts.
Page 86: Delayed Branch Strategies
Explanation of Delayed Branch Methodology:
Including reorder impacts to facilitate efficient execution cycles.
Page 87: Effective Use of Delayed Branches
Overview of Delayed Instruction Techniques:
Instruction slot utilization shown through examples.
Page 88: Delayed Branch Techniques Explained
Behavioral Patterns for Reducing Inductions:
Techniques for placing useful instructions in delay slots or NOPs.
Page 89: Static Branch Prediction Techniques
Hazard Management through Prediction Approaches:
Examination of execution ahead of certain instruction cycles.
Page 90: Dynamic Branch Prediction Techniques
Responsive Prediction Management:
Techniques to adjust predictions based on execution history.
Page 91: Robust Prediction Structures
Performance Impacts of More Complex Prediction Algorithms:
Improvements over simpler methods.
Page 92: Instruction Set Influences on Pipelining
Effects of Instruction Design on Performance:
Adaptations in instruction style to enhance effectiveness.
Page 93: System Characteristics for Memory Management
Features of Easy Operand Access in Instructions:
Examples showcasing optimal instructions setups.
Page 94: Data Path and Register Considerations
Overview of Control Mechanisms:
Efficient management involving various signal paths.
Page 95: Pipelined Data Path Design
Illustrating Features of Pipelined Execution:
Architecture confirmed through detailed diagram descriptions.
Page 96: Control Structure During Pipelined Execution
Further Development of Control Architecture:
Detailed specs for signal management and operations.
Page 97: Superscalar Operations Overview
Performance through Multiple Issue Capabilities:
Indication of execution throughput from multiple instructions/concurrency.
Page 98: Timing and Process Execution in Superscalar Systems
Relaying the Instruction Execution Flow:
Timing per instruction across execution pipelines visualized.
Page 99: Flow Completion in Superscalar Operations
Commitment of Execution Processes:
Using temporary registers for efficient command completions.
Page 100: Performance Considerations for Execution Completion
Managing Throughput and Exceptions:
Outlining the timing and process efficiency needs.
Page 101: Performance Measurement and Goals
Key Performance Indicators of Pipelining:
Dynamic instruction monitoring and associated metrics.
Page 102: Execution Timing Considerations
Key Metrics in Execution Timing and Instructions:
Overall program timing factors included in performance.
Page 103: Pipelining and Throughput Calculation
Questions Surrounding Pipeline Efficiency:
Queries on adequate design and performance metrics.
Page 104: Considerations for Pipeline Stage Design
Pipelining Stage Optimization:
Evaluation of increasing delays alongside throughput variations.