Pentium Microprocessor Architecture and X86 Programming Study Notes

Comparison Between Microprocessors and Microcontrollers

• Microprocessor Characteristic Details:

  • Internal Composition: Consists exclusively of a Central Processing Unit (CPU).
  • System Architecture: Integrated as only a processor; requires external connection of memory (RAM/ROM) and I/O components.
  • Primary Applications: Used predominantly in Personal Computers, accounting systems, game machines, and complex industrial controllers.
  • Usage Context: Suitable for general-purpose applications that require handling massive amounts of data.
  • Complexity and Cost: Highly complex and expensive, featuring a large instruction set for diverse processing tasks.
  • Examples: Computation systems, simulators, and standard desktop PCs.

• Microcontroller Characteristic Details:

  • Internal Composition: Contains a CPU, memory, and I/O components all integrated onto a single silicon chip.
  • System Architecture: An autonomous system with internal memory and I/O; essentially an "embedded system on a chip."
  • Primary Applications: Used in application-specific systems such as washing machines, MP3 players, microwave ovens, and cameras.
  • Usage Context: Optimized for specific tasks requiring efficient, localized control.
  • Complexity and Cost: Simple and inexpensive with a reduced instruction set optimized for specific control operations.
  • Examples: Mobile phones, automobiles, CD/DVD players, security alarms, keyboard controllers, and digital watches.

Architecture of the Legacy 8086 Microprocessor

• Hardware Specifications:

  • It is a $16$-bit microprocessor.
  • Address Bus: $20$-bit address line, allowing for a memory capacity of $1\,MB$ ($2^{20} = 1,048,576\,\text{bytes}$).
  • Data Bus: $16$-bit data bus.
  • Clock Speed: Ranges between $5\,MHz$, $8\,MHz$, and $10\,MHz$ depending on the version.
  • Operating Modes: Supports Minimum and Maximum modes.
  • Structural Support: Supports memory segmentation and pipelining.

• 8086 Functional Units:

  • Execution Unit (EU): Responsible for decoding and executing instructions. It provides instructions to the BIU regarding where to fetch data but has no direct connection to system buses; it communicates data through the BIU. It controls operations on data using the instruction decoder and Arithmetic Logic Unit (ALU).
  • Bus Interface Unit (BIU): Manages all data and address transfers on the buses for the Execution Unit.

• 8086 General Purpose Registers:

  • AX (Accumulator): Used to store operands for arithmetic operations.
  • BX (Base Register): Used to store the starting base address of the memory area within the data segment.
  • CX (Counter): Used as a loop counter in loop instructions.
  • DX (Data Register): Used to hold I/O port addresses for I/O instructions.

• 8086 Pointer and Index Registers:

  • Instruction Pointer (IP): A $16$-bit register holding the offset of the next instruction in the Code Segment; it increments after every byte fetch.
  • Stack Pointer (SP): Points to the top of the stack within the Stack Segment; used in PUSH, POP, CALL, and RET instructions.
  • Base Pointer (BP): Holds offset addresses of any location in the stack segment for random access.
  • Source Index (SI): Holds the offset address in the Data Segment during string operations.
  • Destination Index (DI): Holds the offset address in the Extra Segment during string operations.

• 8086 Segment Registers:

  • Code Segment (CS): Holds the base address for programs.
  • Data Segment (DS): Holds the base address for data.
  • Stack Segment (SS): Holds the base address for the stack.
  • Extra Segment (ES): Holds the base address for additional data storage.

8086 Flag Register and Status Monitoring

• General Format: A $16$-bit register where $9$ bits are used as active flags to recognize or change the processor state.
• Status Flags:
  • Carry Flag (CF): Set if there is a carry out of the Most Significant Bit (MSB); indicates overflow for arithmetic.
  • Parity Flag (PF): Set if the lower order $8$ bits of the result contain an even number of $1$'s.
  • Auxiliary Carry Flag (AF): Set if there is a carry/borrow from the lower nibble ($D_0-D_3$) to the upper nibble ($D_4-D_7$); specifically bit $D_3$ to $D_4$.
  • Zero Flag (ZF): Set to $1$ if the result of an arithmetic or logical operation is zero.
  • Sign Flag (SF): Sets based on the MSB of the result ($1$ for negative, $0$ for positive).
  • Overflow Flag (OF): Set when the result exceeds the system capacity.
• Control Flags:
  • Trap Flag (TF): Enables single-step mode for debugging; allows executing one instruction at a time.
  • Interrupt Enable Flag (IF): If set to $1$, external interrupts are enabled; if $0$, they are prohibited.
  • Direction Flag (DF): Controls string processing direction. If set, strings are accessed from high to low memory address; if reset, low to high.

Memory Segmentation and Address Calculation

• Segmentation Logic: The memory is divided into segments to allow the $16$-bit registers to address a $20$-bit physical space.
• Physical Address Characteristics:
  • Range: $00000H$ to $FFFFFH$.
  • Each segment is $64\,KB$ in size.
  • Segment registers store only the upper $16$ bits of the starting address.
• Calculation Process:
  • Logical Address Format: $\text{Base Address} : \text{Offset}$.
  • The Physical Address is obtained by shifting the Segment (Base) address left by $4$ bits (multiplying by $10H$) and adding the Offset.
  • Example Calculation:
    • Segment Address: $1005H$ ($0001\,0000\,0000\,0101$)
    • Shifted Segment: $10050H$ ($0001\,0001\,0000\,0101\,0000$)
    • Offset Address: $5555H$
    • Physical Address: $155A5H$ ($10050H + 5555H$)

Addressing Modes in the 8086 Microprocessor

• Register Mode: Both operands are registers (e.g., MOV AX, BX).
• Immediate Mode: Data operand is part of the instruction (e.g., MOV AX, 2000).
• Direct Mode: Effective address (displacement) is directly provided in the instruction (e.g., MOV AX, [0500]).
• Register Indirect Mode: Effective address is held in a register ($BX, SI, DI$ for $16$-bit segments) (e.g., ADD AX, [BX]).
• Based Mode: Effective address = Base Register ($BX$ or $BP$) + Displacement (8 or 16 bit) (e.g., MOV AL, [BP + 0100]).
• Indexed Mode: Effective address = Index Register ($SI$ or $DI$) + Displacement (e.g., MOV AX, [SI + 2000]).
• Based Indexed Mode: Effective address = Base Register + Index Register (e.g., MOV AX, [BX + SI]).
• Based Indexed Displacement Mode: Effective address = Base Register + Index Register + Displacement (e.g., MOV AL, [SI + BP + 2000]).

Fundamentals of the Pentium Microprocessor Architecture

• Origins and Evolution: Originates from the 80486; represents a family sharing a common architecture.
• Key Specifications:
  • Architecture: $32$-bit Microprocessor.
  • Data Bus: $64$-bit bus with $8$ memory banks.
  • Address Bus: $32$-bit bus, capable of accessing $4\,GB$ of physical memory.
  • Transistor Count: $3,100,000$ transistors.
  • Release Date: $1993$.
  • Frequency Range: Operates between $66\,MHz$ and $200\,MHz$ (specific iterations: 75, 90, 100, 120, 133, 150, 166, 200 MHz).
• Superscalar Performance:
  • Utilizes a 2-way superscalar architecture.
  • Features two parallel integer pipelines: the U-pipe and the V-pipe.
  • Integer Pipeline Stages ($5$ Stages):
    1. PF (Prefetch)
    2. D1 (First Decode)
    3. D2 (Second Decode/Address Translation)
    4. EX (Execute)
    5. WB (Write Back)
  • Floating Point Unit (FPU): Internal unit with an $8$-stage FPU pipeline and $80$-bit FP registers.
• Cache and Optimization:
  • L1 Cache: Separate on-chip $8\,KB$ Code Cache and $8\,KB$ Data Cache (Harvard architecture).
  • Branch Prediction: Logic utilizing a $256$-entry Branch Target Buffer (BTB).

Functional Units of the Pentium Processor

• Bus Unit: Transfers data in/out of the processor and connects to external memory/IO via the system bus.
• L1 Code Cache: $8\,KB$, 2-way set associative; stores recently used instructions.
• Prefetch Unit: Fetches instructions from code cache. Features two $32$-byte queues (one active, one for branch prediction).
• Decode Unit:
  • Decodes two instructions simultaneously for the U and V pipes.
  • Hardwired Control: Decodes simple instructions.
  • Micro-programmed Control (Control ROM): Decodes complex instructions.
• Integer Execution Unit:
  • Features separate ALUs for U and V pipes ($32$-bit each).
  • U-pipe Specialization: Includes a barrel shifter for complex arithmetic like MUL and DIV.
  • Each pipe has its own address generation unit.
• Floating Point Unit: Dedicated control unit and independent circuits for FP operations.
• Advanced Programmable Interrupt Controller (APIC): Manages interrupt requests from external devices.
• System Management Mode (SMM): Controls power usage for the processor and peripherals.

Pentium Operating Modes and Pipelines

• Operating Modes:
  1. Protected Mode: Recommended mode; all architectural features and privilege levels ($4$ levels) are available for maximum performance.
  2. Real-Address Mode: Simulates the 8086 environment with extensions; the processor enters this mode upon Reset.
• Pipeline Stage Details:
  • D1 (First Decode): Generates a control word and attempts to pair two instructions to run in parallel.
  • D2 (Second Decode): Decodes the control word, performs segment/page translation, and calculates memory operand physical addresses. Performs protection checks.
  • EX (Execute): Accesses data cache and performs ALU operations. Both pipes can access data cache simultaneously. If the U-pipe stalls, the V-pipe must stall; if the V-pipe stalls, the U-pipe can continue.
  • WB (Write Back): Updates registers and flags with the final result.

Instruction Pairing Rules (Issue Algorithm)

• Pairing Conditions for I1 (U-pipe) and I2 (V-pipe):
  • Both I1 and I2 must be "Simple" instructions.
  • I1 must not be a Jump instruction.
  • Resource Dependencies: Destination of I1 cannot be the Source or Destination of I2 (prevents RAW and WAW contentions).
• Constraints:
  • Shift/Rotate: Can only pair in the U-pipe.
  • ADC and SBB: Can only pair in the U-pipe.
  • JMP, CALL, and Jcc: Can only pair in the V-pipe.
  • Operands: Neither instruction can contain both a displacement and an immediate operand simultaneously.

Branch Prediction Logic and BTB

• The Problem of Flushing: Program transfer instructions (JMP, CALL, RET) deviate from sequential execution, causing instructions already in the pipeline to become invalid ("bubbles"). This requires flushing the pipeline.
• Dynamic Branch Prediction: Pentium predicts whether a branch will be "Taken" or "Not Taken."
  • If correct: No cycles lost.
  • If incorrect: Pipeline is flushed and reloaded.
• Branch Target Buffer (BTB):
  • A 4-way set-associative look-aside cache with $256$ entries.
  • Entry Contents: Valid bit, History bits, Source memory address, and Target address.
  • History States:
    • $11$: Strongly Taken
    • $10$: Weakly Taken
    • $01$: Weakly Not Taken
    • $00$: Strongly Not Taken
• Prediction Logic:
  • BTB Miss: If the instruction is new, it is predicted "Not Taken."
  • BTB Hit: If history bits are $10$ or $11$, it is predicted "Taken." The prefetcher switches to the second queue (target address). If history bits are $00$ or $01$, it is predicted "Not Taken."

Pentium Programmer's Model and Register Set

• Multipurpose Registers ($32$-bit):
  • EAX (Accumulator): Multiplication, division, adjustment instructions.
  • EBX (Base Index): Holds offset addresses for memory data.
  • ECX (Count): Loop and instruction counter.
  • EDX (Data): Holds results of multiplication or dividends for division; can address I/O ports.
  • EBP (Base Pointer): Points to memory data transfers, often in the stack.
  • EDI (Destination Index): String destination addressing.
  • ESI (Source Index): String source addressing.
• Special-Purpose Registers:
  • EIP (Instruction Pointer): $32$-bit register pointing to the next instruction.
  • ESP (Stack Pointer): Addresses the stack area.
  • EFLAGS: $32$-bit register containing Status, Control, and System flags.
• Segment Registers: $CS$ (Code), $DS$ (Data), $SS$ (Stack), $ES$ (Extra), $FS$, and $GS$ (Supplemental segments often used by OS for thread-specific or CPU-specific data).
• System Flags in EFLAGS:
  • AC (Alignment Check): Set if unaligned memory access occurs.
  • ID (Identification): Indicates support for the CPUID instruction.
  • RF (Resume): Disables debug exceptions temporarily.
  • IOPL (I/O Privilege Level): Controls I/O access in protected mode.
  • VM (Virtual 8086 mode): Enables/disables 8086 emulation.

Pentium Memory and Cache Organization

• Data Types: Integers ($8, 16, 32$-bit), Characters (ASCII), and Floating Points (Single, Double, and Extended precision).
• Pentium Addressing Modes (32-bit):
  • Formula: $\text{Target Address} = \text{Base Register} + (\text{Index Register} \times \text{Scaling Factor}) + \text{Displacement}$.
  • Scaling Factors: $1, 2, 4, 8$.
  • Displacement: $0, 8, 32$ bits.
• L1 Cache Management:
  • Ways: Divided into equal sections called "cache ways."
  • Mapping: Set-associative mapping allows a block of main memory to map to one particular set.
  • Modes:
    • Write-through: Updates main memory immediately on every write.
    • Write-back: Acts as a buffer; writes to main memory only when the bus is available or a line is replaced (using the NW bit).
  • Data Integrity: Triple-ported tags for U/V pipes and Bus Snooping. Parity bits are used for every byte in the data cache and every $8$ bytes in the instruction cache.
  • Translation Lookaside Buffer (TLB): Separate TLBs for data ($64$ entries for $4\,KB$ pages, $8$ entries for $4\,MB$ pages) and code ($32$ entries).

Instruction Set Details and Assembly Language Programming

• Transfer Instructions:
  • MOVZX/MOVSX: Move with Zero/Sign extension.
  • BSWAP: Reverses byte order (Endian conversion).
  • XCHG: Exchange data between locations.
  • LEA: Load Effective Address.
• Arithmetic and Logic:
  • ADC/SBB: Add/Subtract with Carry/Borrow.
  • NEG: 2's complement negation.
  • MUL/IMUL: Unsigned/Signed multiplication. Result for $32$-bit is in EDX:EAX.
  • DIV/IDIV: Unsigned/Signed division. Dividend must be double the size of the divisor.
  • CBW/CWD/CDQ: Sign extension (Byte to Word, Word to Double, Double to Quadword).
  • CMPXCHG: Compare and Exchange; compares accumulator with destination.
  • XADD: Adds and then exchanges the original destination value into the source.
• Bit Manipulation:
  • BT (Test), BTC (Test and Complement), BTR (Test and Reset), BTS (Test and Set).
  • BSF/BSR: Bit Scan Forward/Reverse.
• Processor Control:
  • CPUID: Returns vendor and model info.
  • STC/CLC: Set/Clear Carry Flag.
  • STD/CLD: Set/Clear Direction Flag.
• Arrays and Strings:
  • Arrays are allocated using DW (Define Word), DB (Define Byte), or DD (Define Doubleword).
  • DUP: Used for repeating values (e.g., 4 DUP(2) results in 2, 2, 2, 2).
  • REP: Prefix to repeat string instructions until CX = 0.
• System Calls (Linux/NASM):
  • int 0x80: Kernel interrupt.
  • eax = 4: sys_write.
  • eax = 3: sys_read.
  • eax = 1: sys_exit.