Comprehensive Study Guide on Computer Processors and Architecture

Components and Organization of a Computer

• The computer consists of three primary components:

  • 1. Processor
  • 2. Memory
  • 3. Input/Output (I/O) devices

• The Central Processing Unit (CPU) is characterized as the “brain” of the computer. Its primary function is to execute programs stored in the main memory by performing three specific actions in sequence:

  • Fetching instructions.
  • Examining (decoding) instructions.
  • Executing instructions one after another.

• The internal organization of a simple computer connects the following elements via a bus:

  • Central Processing Unit (CPU): Contains the Control Unit (CU), Arithmetic Logic Unit (ALU), and Registers.
  • Main Memory.
  • I/O Devices: Includes items such as the disk, printer, and other peripherals.

CPU Parts and Internal Memory

• Control Unit (CU): This component is responsible for the process of fetching instructions from the main memory.

• Arithmetic Logic Unit (ALU): This unit performs the operations required to carry out instructions, such as addition and Boolean AND operations.

• Registers: These are small, high-speed memory units located inside the CPU. They are used for storing temporary results and information. Because they are internal to the CPU, they can be read from and written to at extremely high speeds. Key registers include:

  • Program Counter (PC) or Instruction Pointer (IP): This is the most important register; it points to the address of the next instruction specifically designated to be fetched for execution.
  • Instruction Register (IR): This register holds the specific instruction that is currently being executed.

Von Neumann Architecture and Its Limitations

• The simple von Neumann CPU architecture consists of several interconnected parts:

  • The Central Processing Unit containing the Control Unit, Arithmetic Logic Unit, and Registers.
  • Registers include the Memory Address Register (MAR), Memory Data Register (MDR), Program Counter (PC), and Accumulator (Acc).
  • Input and Output interfaces.
  • Memory, which stores both Data and Programs.

• The Functioning of the Von Neumann Architecture:

  • The CPU continuously repeats a three-step cycle: Fetch, Decode, and Execute.
  • Fetch: The CPU retrieves an instruction from memory. For example, if the instruction is "ADD two numbers," the Program Counter indicates the memory location of this instruction.
  • Decode: The Control Unit interprets the fetched instruction. In the addition example, it determines that the specific operation required is addition.
  • Execute: The CPU performs the instruction. In this case, the ALU adds the two numbers. After completion, the cycle repeats.

• Example: Adding Two Numbers (ADD 5 + 10):

  • Memory stores the instruction and the numbers 5 and 10.
  • CPU fetches the "ADD" command.
  • Control Unit decodes the command.
  • ALU performs the calculation $5 + 10$.
  • The result ($15$) is stored back in memory or a register.
  • Output displays the result as $15$.

• Limitation of Von Neumann Architecture:

  • Because instructions and data share the same memory path, the CPU is unable to fetch data and instructions simultaneously. This is often referred to as a bottleneck that can slow down processing.
  • Modern computers address this limitation using:
  • Cache memory.
  • Multiple cores.
  • Modified Harvard architecture, which utilizes separate instruction and data caches.

Detailed Fetch, Decode, and Execute Cycles

• The Fetch Process:

  • The CPU identifies where the next instruction is located using two specific registers: the Code Segment (CS) and the Instruction Pointer (IP).
  • These registers work together to form a Physical Address using the following formula:
  • $Physical Address = CS \times 10h + IP$
  • Example Calculation:
  • Given $CS = 2000h$
  • Given $IP = 0100h$
  • Calculation: $2000h \times 10h = 20000h$ and $20000h + 0100h = 20100h$.
  • The CPU reads the instruction at address $20100h$.
  • Once fetched, the Program Counter is incremented to point to the next memory location for the subsequent cycle.

• Instruction Processing Components:

  • Bus Interface Unit (BIU): Communicates with memory and I/O devices. Its responsibilities include fetching instructions, reading/writing data from/to memory, generating physical addresses, and managing the instruction queue. It contains registers: CS, DS, SS, ES, IP, and the instruction queue.
  • Execution Unit (EU): Executes instructions previously fetched by the BIU. Its responsibilities include decoding instructions, performing arithmetic and logical operations, updating registers, and updating flags.

• The Decode Process:

  • The CPU examines the contents of the Instruction Register (IR) to identify the operation and the registers or memory locations involved.
  • The CPU interprets the Opcode (operation code) and operands.
  • Example: For the machine code $B8\,34\,12$
  • The decoder recognizes $Opcode = B8$, which stands for mov ax, imm16.
  • It identifies the next two bytes ($34\,12$) as the immediate value $1234h$.
  • The complete instruction is interpreted as MOV AX, 1234H.

• The Execute Process:

  • The EU performs the arithmetic, logic, or memory access operation specified.
  • Example: MOV AX, 1234H
  • Before execution: $AX = 0000h$
  • After execution: $AX = 1234H$

Machine Code Execution Example

• Consider the following source code and machine code trace at Code Segment $2000h$:

  • Address $20100h$ (offset 0100h): Machine code B8 34 12. Source: mov ax, 1234h. Result: $AX = 1234H$.
  • Address $20103h$ (offset 0103h): Machine code BB 21 43. Source: mov bx, 4321h. Result: $BX = 4321H$.
  • Address $20106h$ (offset 0106h): Machine code 03 C3. Source: add ax, bx. Result: $AX = 1234H + 4321H = 5555H$.
  • Address $20108h$ (offset 0108h): Machine code C3. Source: ret. Action: Return to caller.

• Sequential Execution vs. Branching:

  • Sequential Execution: Instructions follow a linear order (e.g., 0100 → 0103 → 0106). The IP moves forward automatically.
  • Branching Instructions: These change the normal sequence. Examples include JMP, CALL, RET, LOOP, JE (Jump if Equal), JNE (Jump if Not Equal), JG (Jump if Greater), and JL (Jump if Less).
  • Branching Example: If a JMP SKIP instruction is placed after mov ax, 1234h, the instruction mov bx, 4321h is skipped entirely and never executed.

Pipelining Techniques

• Pipelining is a computer architecture technique that improves throughput and processing speed by breaking down instruction execution into multiple stages. Overlapping these stages allow multiple instructions to be processed simultaneously at different stages of completion.

• Five-Stage Pipeline Model:

  • 1. Fetch: Get the instruction from memory using the address in the Program Counter.
  • 2. Decode: Determine the operation and operands; identify required functional units.
  • 3. Execute: Perform arithmetic, logical, or memory access operations.
  • 4. Memory Access: Read from or write to memory if the instruction requires it (e.g., load/store).
  • 5. Write Back: Save the final result into a register or memory location.

• Comparison of Execution Models:

  • Non-Pipelined CPU: Finishes one full instruction before starting the next. Steps are sequential and CPU parts may sit idle, leading to lower throughput.
  • Pipelined CPU: Works on multiple instructions simultaneously through overlapping stages. CPU parts are used more efficiently, resulting in higher instruction throughput despite a more complex hardware design.

Multicore Processing and Parallelism

• Multicore Architecture: A multicore CPU contains multiple independent CPU cores within a single processor package. Each core has its own pipeline.

  • Example: A single core can handle multiple instructions at different stages (Fetch, Decode, Execute, etc.). A multicore processor (e.g., 4 cores) can assign separate tasks to each core, such as Core 1 handling a browser, Core 2 handling music, and Core 3 handling a word processor.

• Processor-Level Parallelism (PLP): This refers to using multiple processing units or cores concurrently to execute instructions.

  • Multicore is the hardware structure, while PLP is the ability or result of utilizing that hardware to perform work simultaneously.
  • Instruction-Level Parallelism (ILP): Executing multiple instructions simultaneously within a single processor core.
  • Thread-Level Parallelism (TLP): Executing multiple threads or processes simultaneously across multiple processor cores.

• Difference Table: Pipelining vs. Multicore

  • Pipelining: Improves one CPU core; works by overlapping stages; provides instruction-level parallelism; uses one instruction stream.
  • Multicore: Adds more CPU cores; works by running separate tasks; provides thread/task-level parallelism; uses multiple instruction streams; allows more tasks to be executed simultaneously.

Applications of Parallelism

• Parallelism is utilized across a wide variety of modern computing systems:
  • 1. Desktop and Laptop Computers: Use multi-core processors for multitasking and daily productivity.
  • 2. Server Systems: Employ multi-core or multiple processors in parallel to handle client requests and data processing in data centers and cloud environments.
  • 3. Supercomputers and HPC Clusters: Use thousands or millions of cores for complex simulations, weather forecasting, and scientific research.
  • 4. Graphics Processing Units (GPUs): Specialized parallel processors with many small cores designed for 3D rendering, machine learning, and AI.
  • 5. Smartphones and Tablets: Leverage multi-core processors for responsiveness in gaming and multimedia.
  • 6. Gaming Consoles: Devices like the PS5, Xbox Series X, PS4, Xbox One, and Nintendo Switch use multi-core CPUs and GPUs for graphics, physics (AI) simulations, and immersive experiences.
  • 7. Networking Equipment: Routers and switches use parallelism to process data packets simultaneously for efficient routing.
  • 8. AI and Machine Learning Accelerators: Specialized hardware like Tensor Processing Units (TPUs) and Neural Processing Units (NPUs) process neural network computations in parallel.
  • 9. Embedded Systems: Used in automotive control, robotics, and industrial automation for real-time control.
  • 10. Scientific Instruments: Incorporate parallelism to analyze experimental data and simulations rapidly.