Computer Architecture and Engineering Study Guide

Memory Systems Architecture and Design

• Memory Interleaving and Bandwidth Improvement

  • Definition: Memory interleaving is a design technique that divides main memory into multiple independent memory modules or banks ($M_0, M_1, \text{...}, M_{n-1}$) that can be accessed concurrently.
  • Low-Order Interleaving: The least significant bits (LSBs) of the memory address select the memory module, while the most significant bits (MSBs) select the memory location within that module. This arrangement distributes consecutive memory addresses sequentially across different modules.
  • High-Order Interleaving: The MSBs select the module, and the LSBs select the offset within the module, organizing memory into contiguous blocks per module.
  • Bandwidth Improvement Mechanics:
  • Overlapped Access: Allows pipelined memory requests. While one memory module is in its refresh or read/write recovery cycle, another module can begin servicing the next sequential address request.
  • Latency Hiding: Reduces effective memory latency by masking access delays through concurrency.
  • Throughput Multipliers: If an interleaved memory system consists of $N$ modules and the memory bus supports parallel transfers, memory bandwidth can theoretically scale up by a factor of $N$.

• Design of a $16\text{K} \times 8$ Memory System Using $4\text{K} \times 4$ Chips

  • System Specifications:
  • Target capacity: $16\text{K} \text{ words} = 16,384 \text{ locations}$.
  • Word size: $8\text{ bits}$.
  • Available chip capacity: $4\text{K} \times 4\text{ bits} = 4,096 \text{ locations} \times 4\text{ bits}$.
  • Chip Count Calculation:
  • Capacity ratio per row (word length extension): $\frac{8\text{ bits}}{4\text{ bits}} = 2\text{ chips per bank}$.
  • Address depth ratio (capacity extension): $\frac{16\text{K}}{4\text{K}} = 4\text{ banks (rows)}$.
  • Total number of chips required: $4 \text{ rows} \times 2 \text{ chips/row} = 8\text{ chips}$.
  • Address Bus Decoding Details:
  • Total system address lines required: $16\text{K} = 2^{14} \rightarrow 14\text{ address lines } (A_{13} \text{ to } A_0)$.
  • Internal chip address lines: $4\text{K} = 2^{12} \rightarrow 12\text{ address lines } (A_{11} \text{ to } A_0)$.
  • Bank selection lines: $14 - 12 = 2\text{ high-order address lines } (A_{13}, A_{12})$.
  • Decoding Architecture:
  • A $2\text{-to-}4$ binary decoder receives address lines $A_{13}$ and $A_{12}$ as inputs to generate $4$ Chip Enable ($\text{CE}_0, \text{CE}_1, \text{CE}_2, \text{CE}_3$) signals.
  • Output $\text{CE}_0$ enables Bank 0 (Chips 0 and 1, addressing range $\text{0x0000}$ to $\text{0x0FFF}$).
  • Output $\text{CE}_1$ enables Bank 1 (Chips 2 and 3, addressing range $\text{0x1000}$ to $\text{0x1FFF}$).
  • Output $\text{CE}_2$ enables Bank 2 (Chips 4 and 5, addressing range $\text{0x2000}$ to $\text{0x2FFF}$).
  • Output $\text{CE}_3$ enables Bank 3 (Chips 6 and 7, addressing range $\text{0x3000}$ to $\text{0x3FFF}$).
  • Data Bus Interfacing:
  • Low-order address bus lines $A_{11} \text{ through } A_0$ connect directly in parallel to the internal address lines of all $8$ chips.
  • Within each bank, Chip A outputs supply data bits $D_3 \text{ through } D_0$, and Chip B outputs supply data bits $D_7 \text{ through } D_4$, forming the full $8\text{-bit}$ data bus.

• Differentiation of Non-Volatile Semiconductor Memory Technologies

  • ROM (Read-Only Memory): Mask-programmed during silicon fabrication. Data is permanently burnt into the physical layout; cannot be erased or modified post-manufacture.
  • PROM (Programmable Read-Only Memory): Shipped unprogrammed. Uses fusible links or anti-fuses that are permanently blown using a high-voltage PROM programmer. Can be programmed only once.
  • EPROM (Erasable Programmable Read-Only Memory): Uses floating-gate transistors. Programmable electronically; erasable by exposing the quartz window on top of the package to high-intensity ultraviolet (UV) light for 10-20 minutes. UV light clears all contents uniformly.
  • EEPROM (Electrically Erasable Programmable Read-Only Memory): Uses floating-gate structures with thin oxide layers allowing field-effect byte-by-byte electrical erasing and reprogramming without removal from the circuit board.
  • Flash Memory: A specialized variant of EEPROM with higher density and faster operational speeds. Erases data in larger blocks or sectors rather than individual bytes, utilizing Fowler-Nordheim tunneling or hot-carrier injection.

• Endianness and Byte Ordering Schemes

  • Endianness Concept: Refers to the order in which individual bytes of a multi-byte word are stored in consecutive memory addresses.
  • Big-Endian: Stores the Most Significant Byte (MSB) at the lowest memory address (smallest numerical address).
  • Little-Endian: Stores the Least Significant Byte (LSB) at the lowest memory address.
  • Storage Example for 32-bit Value $\text{0x12345678}$:
  • MSB = $\text{0x12}$, LSB = $\text{0x78}$.
  • Assuming base memory address $A$:
  • Big-Endian Representation:
    • Address $A+0$: $\text{0x12}$
    • Address $A+1$: $\text{0x34}$
    • Address $A+2$: $\text{0x56}$
    • Address $A+3$: $\text{0x78}$
  • Little-Endian Representation:
    • Address $A+0$: $\text{0x78}$
    • Address $A+1$: $\text{0x56}$
    • Address $A+2$: $\text{0x34}$
    • Address $A+3$: $\text{0x12}$

Instruction Set Architectures and Assembly Programming

• Comparison of Instruction Address Formats

  • Three-Address Format:
  • Syntax: OPCODE DST, SRC1, SRC2
  • Explicitly specifies two source operands and one destination operand.
  • Minimizes instruction count per program at the expense of longer instruction bit-lengths.
  • Two-Address Format:
  • Syntax: OPCODE DST_SRC1, SRC2
  • Destination field doubles as one of the source operands, causing the original value in the destination to be overwritten.
  • Reduces instruction bit-width while maintaining register flexibility.
  • One-Address Format (Accumulator Architecture):
  • Syntax: OPCODE SRC
  • Implicitly uses a dedicated internal processor register called the Accumulator ($\text{ACC}$) as both one source operand and the destination.
  • Instruction length is short since only one address or register code is specified.
  • Zero-Address Format (Stack Architecture):
  • Syntax: OPCODE
  • Operates implicitly on the top entries of an evaluation stack (Top of Stack: $\text{TOS}$, Next on Stack: $\text{NOS}$).
  • Operands are pushed onto the stack prior to execution and popped upon completion, resulting in extremely compact instruction encodings.

• Evaluation of $X = (A + B) \times (C - D)$ Across Instruction Formats

  • Three-Address Format:
  • ADD T1, A, B ; Memory/Register $T1 \text{ gets } A + B$
  • SUB T2, C, D ; Memory/Register $T2 \text{ gets } C - D$
  • MUL X, T1, T2 ; Memory/Register $X \text{ gets } T1 \times T2$
  • Two-Address Format:
  • MOVE R1, A ; $R1 \text{ gets } A$
  • ADD R1, B ; $R1 \text{ gets } R1 + B$
  • MOVE R2, C ; $R2 \text{ gets } C$
  • SUB R2, D ; $R2 \text{ gets } R2 - D$
  • MUL R1, R2 ; $R1 \text{ gets } R1 \times R2$
  • MOVE X, R1 ; $X \text{ gets } R1$
  • One-Address Format (Accumulator):
  • LOAD A ; $\text{ACC} \text{ gets } A$
  • ADD B ; $\text{ACC} \text{ gets } \text{ACC} + B$
  • STORE T1 ; $T1 \text{ gets } \text{ACC}$
  • LOAD C ; $\text{ACC} \text{ gets } C$
  • SUB D ; $\text{ACC} \text{ gets } \text{ACC} - D$
  • MUL T1 ; $\text{ACC} \text{ gets } \text{ACC} \times T1$
  • STORE X ; $X \text{ gets } \text{ACC}$
  • Zero-Address Format (Stack):
  • PUSH A ; Push $A$ to Stack
  • PUSH B ; Push $B$ to Stack
  • ADD ; Pop $A$ and $B$, Push $(A + B)$
  • PUSH C ; Push $C$ to Stack
  • PUSH D ; Push $D$ to Stack
  • SUB ; Pop $C$ and $D$, Push $(C - D)$
  • MUL ; Pop $(A + B)$ and $(C - D)$, Push $(A + B) \times (C - D)$
  • POP X ; Pop top of stack into memory location $X$

• Calculation of Minimum Instruction Length

  • Given Parameters:
  • Number of opcodes: $60$
  • Number of registers: $16$
  • Memory address field size: $12\text{ bits}$
  • Field Bit-Width Calculations:
  • Bits needed for Opcode field: $\text{Bits} = \rceil \text{log}_2(60) \rceil = 6\text{ bits}$ ($2^5 = 32 < 60 \text{ and } 2^6 = 64 \text{ bits}$).
  • Bits needed for Register field: $\text{Bits} = \text{log}_2(16) = 4\text{ bits}$.
  • Bits needed for Memory Address field: $12\text{ bits}$.
  • Total Minimum Instruction Length:
  • $\text{Length} = \text{Opcode Bits} + \text{Register Bits} + \text{Address Bits}$
  • $\text{Length} = 6 + 4 + 12 = 22\text{ bits}$.

• Role and Flags of the Condition Code (Status) Register

  • Role: A status register contains individual 1-bit flags updated by the Execution Unit (ALU) following arithmetic, logical, or data transfer operations. Branch instructions evaluate these flag bits to perform conditional execution.
  • Common Status Flags:
  • Zero Flag ($Z$): Set to $1$ if the result of an operation is numerically equal to zero; cleared to $0$ otherwise.
  • Carry Flag ($C$): Set to $1$ if an arithmetic operation generates a carry out of the most significant bit position during addition, or a borrow during subtraction.
  • Overflow Flag ($V$): Set to $1$ when a signed arithmetic operation produces a result that exceeds the representation range of the destination format (twos-complement overflow).
  • Sign/Negative Flag ($S$ or $N$): Set to $1$ if the most significant bit of the result is $1$, indicating a negative value in signed representation.

Interrupt Handling, Direct Memory Access, and I/O Systems

• Vectored vs. Non-Vectored Interrupts

  • Vectored Interrupts:
  • The interrupting I/O hardware device supplies an Interrupt Vector Index or vector memory address directly to the processor via the data bus during the Interrupt Acknowledge cycle.
  • The CPU retrieves the starting address of the Interrupt Service Routine (ISR) directly from the Interrupt Vector Table (IVT) in memory without scanning I/O devices.
  • High response speed and minimal latency.
  • Non-Vectored Interrupts:
  • The interrupt hardware line routes to a fixed, hardwired memory location regardless of which external hardware device asserted the signal.
  • The CPU must execute a general polling software loop to query every peripheral device sequentially to identify which device triggered the interrupt.

• Interrupt Priority and Nested Interrupt Execution

  • Interrupt Priority Schemes:
  • Hardware Daisy Chaining: A serial hardware bus line passes the Interrupt Acknowledge signal down a line of devices. The device physically closest to the CPU has the highest priority and intercepts the signal first.
  • Parallel Interrupt Controller (e.g., 8259 PIC): Accepts independent hardware interrupt request lines ($\text{IRQ}$) and uses internal priority resolver logic to present only the highest priority active request to the CPU.
  • Nested Interrupt Handling Mechanics:
  • When a higher-priority interrupt occurs while a lower-priority ISR is actively executing, the CPU suspends current ISR execution.
  • The current Program Counter ($\text{PC}$) and Status Register are pushed onto the system stack.
  • The Interrupt Mask Register is updated to block lower or equal priority interrupts while permitting higher priority ones to pass through.
  • Execution jumps to the higher-priority ISR. Upon completion, context is popped from the stack, returning execution to the original lower-priority ISR.

• Direct Memory Access (DMA) Transfer Modes

  • Burst Mode (Block Transfer Mode):
  • The DMA controller acquires complete ownership of the system buses and transfers an entire continuous block of data bytes without yielding control.
  • The CPU is completely halted and isolated from memory until the entire data burst finishes.
  • Cycle Stealing Mode:
  • The DMA controller requests system bus ownership for the duration of a single memory access cycle.
  • Control alternates between the CPU and the DMA controller on a cycle-by-cycle basis, interleaving DMA transfers directly into idle bus states without completely stalling the CPU.
  • Transparent Mode (Hidden DMA):
  • The DMA controller monitors the internal execution state of the CPU and executes transfers only during cycles when the CPU is performing internal operations and is not accessing the external system bus.
  • Eliminates CPU slowdown completely, but restricts transfers to unpredictable idle periods.

• Serial vs. Parallel Communication Systems

  • Serial Communication:
  • Data bits are transmitted sequentially, bit-by-bit, over a single conductor line or differential wire pair.
  • Minimizes cable footprint and eliminates signal skew over long distances.
  • Example: Universal Serial Bus (USB) or Peripheral Component Interconnect Express (PCIe).
  • Parallel Communication:
  • Multiple data bits (e.g., $8, 16, \text{or } 32$ bits) are transmitted simultaneously across parallel bus conductors in a single clock edge cycle.
  • High throughput over short distances, but susceptible to cross-talk, signal noise, and clock skew over long lengths.
  • Example: IEEE 1284 Parallel Printer Port or Parallel ATA (PATA/IDE) interface.

• Memory-Mapped I/O vs. Isolated (Port-Mapped) I/O

  • Memory-Mapped I/O:
  • Peripheral device control, status, and data registers are assigned addresses within the uniform system memory address space.
  • Standard memory access assembly instructions (MOV, LDR, STR) perform I/O reads and writes.
  • Trade-off: Reduces total addressable capacity for system RAM; eliminates the need for distinct control hardware or specialized instruction opcodes.
  • Isolated (Port-Mapped) I/O:
  • Peripheral devices reside in an independent address space separate from physical system RAM.
  • Requires special hardware control signals (e.g., $\text{I/OR}$ and $\text{I/OW}$ vs. $\text{MEMR}$ and $\text{MEMW}$) and dedicated CPU instructions (e.g., IN and OUT in x86 architectures).
  • Trade-off: Preserves the complete main memory space, but requires separate address decoding circuits and instructions.

Modern Processor Architectures and Emerging Trends

• Multicore CPU Architectures vs. Graphics Processing Units (GPUs)

  • Multicore CPUs:
  • Designed with a small number ($2$ to $64$) of highly complex cores engineered for low latency on sequential processing streams.
  • Feature massive speculative execution hardware, aggressive out-of-order execution logic, branch predictors, and large multi-level cache hierarchies ($\text{L1, L2, L3}$).
  • Optimal Workload: Operating system kernels, database management engines, sequential algorithmic tasks.
  • Graphics Processing Units (GPUs):
  • Architected with thousands ($1000+$) of smaller, simpler ALU execution pipelines running under Single Instruction, Multiple Data (SIMD) or Single Instruction, Multiple Threads (SIMT) models.
  • Prioritizes massive total compute throughput over low single-thread latency.
  • Optimal Workload: Dense linear algebra matrix computations, deep learning training models, 3D graphics rendering engines.

• The Power Wall and the Shift to Multicore Processor Designs

  • The Power Wall Problem:
  • Dynamic power consumption in CMOS digital circuits is modeled by the equation:       $P = C \times V^2 \times f$       where $P$ is power, $C$ is active capacitance, $V$ is operating voltage, and $f$ is clock frequency.
  • Increasing single-core performance by scaling clock frequencies ($f$) required raising supply voltage ($V$), causing power consumption and heat dissipation to hit physical thermal envelope limits ($\text{approx. 100-150 Watts per package}$).
  • Architectural Shift to Multicore:
  • Designers ceased scaling clock speeds and instead placed multiple processor cores operating at lower, power-efficient clock frequencies on a single chip die.
  • Thread-level parallelism (TLP) replaced instruction-level parallelism (ILP) as the primary mechanism to scale hardware compute capabilities.

• Speculative Execution Mechanics and Security Vulnerabilities

  • Speculative Execution Concept:
  • Performance optimization technique where the CPU predicts the conditional branch direction using dynamic branch predictors and speculatively executes instructions ahead of execution resolution.
  • If the prediction is correct, the speculatively computed results are committed to architectural registers, preventing execution pipeline stalls.
  • If mispredicted, state changes are discarded and the pipeline flushes the speculatively fetched instructions.
  • Microarchitectural Security Concerns:
  • Speculatively executed path instructions alter the microarchitectural state of the processor before being flushed—most notably by loading speculative data into the hardware CPU caches.
  • Side-Channel Attacks (e.g., Spectre and Meltdown): Attackers measure timing differences in cache accesses (Flush+Reload attacks) to read sensitive kernel or user data that was loaded into the cache during speculative branch execution paths.

• ARM vs. x86 Architectural Design Paradigms

  • ARM Architecture:
  • Based on Reduced Instruction Set Computer (RISC) design principles.
  • Operates on fixed-length instructions (typically 32-bit ARM or 16/32-bit Thumb-2) using a strict load-store model (arithmetic operations apply only to registers).
  • Target Application: Mobile devices, embedded systems, low-power server nodes, Apple Silicon hardware.
  • x86 Architecture:
  • Based on Complex Instruction Set Computer (CISC) design principles.
  • Features variable-length instruction encodings ($1$ to $15$ bytes) and complex hardware memory-to-register instruction operations.
  • Modern x86 processors decode CISC instructions into internal fixed-length micro-operations ($\text{μ-ops}$) hardware-side.
  • Target Application: High-performance desktop computers, enterprise server farms, supercomputing systems.

Comprehensive Analysis of Computer Architecture Evolution, Memory Wall Mitigation, and 8-Bit CPU Design

• Historical Evolution of Computer Architectural Generations

  • First Generation (1940s–1950s):
  • Technology: Vacuum tubes and mercury delay lines / magnetic drums.
  • Characteristics: Machine language operation, immense power draw, physical size, high thermal failures. Example: ENIAC, UNIVAC I.
  • Second Generation (1950s–1960s):
  • Technology: Discrete transistors and magnetic core memory.
  • Characteristics: Introduction of assembly language, early high-level programming languages (FORTRAN, COBOL), improved operating speed and system reliability.
  • Third Generation (1960s–1970s):
  • Technology: Integrated Circuits (ICs)—Small-Scale Integration (SSI) and Medium-Scale Integration (MSI).
  • Characteristics: Emergence of multiprogramming operating systems, standardized Instruction Set Architectures (e.g., IBM System/360 family).
  • Fourth Generation (1970s–Present):
  • Technology: Very Large Scale Integration (VLSI) and Ultra Large Scale Integration (ULSI) microprocessors.
  • Characteristics: Complete CPU on a single silicon chip (Intel 4004 to x86/ARM), massive integration, desktop personal computers, mobile computing.
  • Fifth Generation & Beyond:
  • Technology: Heterogeneous multi-core integration, System-on-Chip (SoC) architectures, Domain-Specific Accelerators (TPUs, NPUs, Quantum Processing Units).

• Architectural Techniques to Bridge the CPU-Memory Speed Gap (The Memory Wall)

  • Multi-Level Hardware Caching Hierarchies:
  • Implementation of fast, small static RAM ($\text{SRAM}$) caches ($\text{L1, L2, L3}$) between the high-speed CPU core and high-capacity dynamic RAM ($\text{DRAM}$) main memory.
  • Exploit principles of Temporal Locality (recently accessed items are likely to be accessed again soon) and Spatial Locality (items near recently accessed addresses are likely to be accessed soon).
  • Hardware and Software Prefetching:
  • Hardware engines analyze address access patterns and speculatively fetch memory blocks into low-latency caches prior to an explicit CPU read request.
  • Non-Blocking / Out-of-Order Caches:
  • Allows the CPU cache to process hit accesses while a previous cache miss is servicing a fill from main memory ("hit-under-miss" operation).
  • Advanced DRAM Interfaces and High-Bandwidth Interconnects:
  • Migration to Synchronous DRAM (SDRAM), Double Data Rate (DDR1-DDR5) buses, and 3D-stacked High-Bandwidth Memory (HBM) architectures connected via silicon interposers.

• Structural Specification and Design Trace of a Simple 8-Bit Paper CPU

  • Internal Registers:
  • Program Counter ($\text{PC}$): $8\text{-bit}$ register holding the memory address of the next instruction to fetch.
  • Accumulator Register ($\text{ACC}$): $8\text{-bit}$ register serving as the primary source/destination operand for ALU operations.
  • Register B ($\text{REG-B}$): $8\text{-bit}$ secondary register supplying the second operand to the ALU.
  • Instruction Register ($\text{IR}$): $8\text{-bit}$ register storing the fetched instruction code.
  • Memory Address Register ($\text{MAR}$): $8\text{-bit}$ register holding memory read/write target addresses.
  • Memory Buffer Register ($\text{MBR}$): $8\text{-bit}$ data hold buffer between CPU buses and external RAM.
  • Flags Register ($\text{FLAGS}$): Contains $1\text{-bit}$ Zero Flag ($Z$) and $1\text{-bit}$ Carry Flag ($C$).
  • Instruction Word Format (8-bit fixed width):
  • Opcode: Upper $4\text{ bits}$ ($\text{Bits } 7 \text{ to } 4$) $\rightarrow 2^4 = 16$ distinct operational codes.
  • Address / Operand: Lower $4\text{ bits}$ ($\text{Bits } 3 \text{ to } 0$) $\rightarrow 2^4 = 16$ direct memory word locations.
  • Internal Architecture Datapath & Control Unit:
  • Single internal $8\text{-bit}$ common data bus interconnecting all system registers, ALU, and MBR.
  • Hardwired Control Logic decoding the Opcode from $\text{IR}$ using a ring counter micro-sequence clock ($T_0, T_1, T_2, T_3$).
  • Execution Trace of Instruction ADD 0x0E (Fetch, Decode, Execute Sequence):
  • Assumed Instruction Bit Encodings: ADD Opcode = $\text{0001}_2$, Target Address = $\text{0E}_{16} = 1110_2$.
  • Phase 1: Fetch Cycles:
    • $T_0$: $\text{MAR} \rightarrow \text{PC}$ (Transfer address from PC to Memory Address Register).
    • $T_1$: $\text{MBR} \rightarrow \text{Memory}[\text{MAR}]$; $\text{PC} \rightarrow \text{PC} + 1$ (Increment Program Counter).
    • $T_2$: $\text{IR} \rightarrow \text{MBR}$ (Transfer fetched instruction word into Instruction Register).
  • Phase 2: Decode Cycle:
    • $T_3$: Control unit decodes upper 4 bits of $\text{IR}$ ($\text{0001}_2$ = ADD), routes lower 4 bits ($1110_2$) to $\text{MAR}$.
  • Phase 3: Execute Cycles:
    • $T_4$: $\text{MBR} \rightarrow \text{Memory}[\text{MAR}]$ (Fetch operand value located at address $\text{0x0E}$ into MBR).
    • $T_5$: $\text{REG-B} \rightarrow \text{MBR}$ (Load operand from MBR to Register B input of ALU).
    • $T_6$: $\text{ACC} \rightarrow \text{ACC} + \text{REG-B}$ (ALU computes sum, stores result back into Accumulator, and updates Zero ($Z$) and Carry ($C$) flags in status register).