In-depth Notes on Instruction Set Architecture

Instruction Set Architecture (ISA)

  • Definition: The Instruction Set Architecture (ISA) defines the operations a computer can perform, their formats, and how to access information in memory.

Purpose of ISA

  • It serves as a contract between programmers and system designers.
  • Allows software to be written independently of hardware, enabling the same programs to run on different architectures (e.g., AMD vs. Intel).

Characteristics of ISA

  • Decouples Software from Hardware: A program compiled for an x86 processor can run on any x86 compatible hardware.
  • Examples: x86, ARM - both are architectures but have different ISAs.

Key Components of ISA

  1. Operations: Specifies the instructions the computer can execute.
  2. Operands: Defines the data operations can act upon, typically locations in memory or registers.
  3. Addressing Modes: Different methods for accessing data, including:
    • Immediate Addressing: Operand is part of the instruction.
    • Absolute Addressing: Full address is specified in the instruction.
    • Register Indirect Addressing: Operand address is stored in a register.
    • Indexed Addressing: Base address plus an offset.

Execution Model and Sequence

  • Von Neumann Architecture: Combines data and instruction memory, sequentially processes instructions.
  • Harvard Architecture: Separates data and instruction memory; typically used in embedded systems.
Execution Steps
  1. Fetch the instruction from memory.
  2. Decode the instruction to understand what operation is needed.
  3. Execute the operation as per the control unit’s directives.
  4. Store the result back to memory or a register.

Endianness

  • Refers to the order of bytes within a data word.
    • Big-endian: Most significant byte stored at the smallest address.
    • Little-endian: Least significant byte stored at the smallest address.
  • Importance: When sharing data between different architectures, knowing the endianness can prevent data misinterpretation.

CISC vs. RISC

CISC (Complex Instruction Set Computer)
  • Has many complex instructions, capable of executing multi-step operations in a single instruction.
  • Example: x86 architecture.
RISC (Reduced Instruction Set Computer)
  • Utilizes simpler instructions, each typically needing one clock cycle to execute.
  • Example: ARM architecture.
Comparison
  • Flexibility: CISC can do more in fewer lines of code, while RISC requires more lines but less complex hardware.
  • Cost: RISC is generally cheaper to implement hardware than CISC.
  • Performance: RISC can be faster due to simpler instructions and execution cycles.

RISC-V Foundation and Ecosystem

  • Open Standard: RISC-V aimed at creating a free and open ISA.
  • Modular Design: Base ISA is relatively small, allows extensions for specific applications.
  • Growing Adoption: Interest in RISC-V is increasing in academia and industry.

Conclusion

  • ISA is crucial in delineating how hardware and software interact, shaping the capabilities and performance of computing systems.