8085 Microprocessor System Study Notes
REVIEW – DESIGN QUESTIONS 1
1. Multiplexing of Address and Data Bus
Reason for Multiplexing:
- The lower order address bus is multiplexed with the data bus to allow an efficient interface with an 8-bit data bus and a 16-bit address bus using only 16 processor connections.De-multiplexing Process:
- Achieved using a latch and the Address Latch Enable (ALE) output from the processor. The ALE acts as a clock signal to the latch:
- When ALE is high (1), the output of the latch is the same as the input (address).
- When ALE is low (0), the data is latched, and the data bus is available for the processor.
2. Status Flags in 8085
Available Flags:
- S (Sign Flag): Indicates positive or negative result from an arithmetic operation.
- Z (Zero Flag): Set if the result is zero.
- AC (Auxiliary Carry Flag): Used in BCD arithmetic.
- P (Parity Flag): Set to indicate even parity.
- CY (Carry Flag): Set if an arithmetic operation generates a carry out.
3. Function of Specific Pins in 8085
ALE (Address Latch Enable):
- Indicates whether the multiplex bus functions as an address bus or a data bus.
- ALE = 1: Multiplex bus functions as address bus.
- ALE = 0: Multiplex bus functions as data bus.
- It enables the latching of the lower order address bus.READY (Input):
- High (1) during a read/write cycle indicates that memory or peripheral is ready to send/receive data. If low (0), the CPU will wait.
- It permits slow peripheral devices more time to access or load data and generate a wait state.
4. Stack Pointer
Definition: A 16-bit register that stores the address of the memory location indicating the top of the stack area.
Use: Helps in managing stack operations such as push and pop.
5. Sub-Routine Code
Given Assembly Code:
ORG 1053H
START: LXI H, LIST
MVI B, 0
MVI A, 0DH
CHKCR: CMP M
JZ DONE
INX H
INR B
JMP CHKCR
DONE: MOV A, B
STA RESULT
RET
LIST: DFB FFH, 41H, 42H, 43H, 44H, 45H, 0DH, 50H
DFB 51H, 52H, 58H, 00H, 0DH
RESULT: DFS 1
```
## REVIEW – DESIGN QUESTIONS 2
### 1. Serial I/O
- **Definition**: Data is transmitted bit by bit.
- **Advantages**:
- Cost reduction technique in data transmission.
- **Communication System**:
- Can be synchronous or asynchronous.
- Includes error corrections/detections like parity check, CRC, etc.
### 2. Checksum Calculation Program
- **Description**: A simple technique for checking data integrity by using checksum calculation for a data block.
- **Program Code**:
assembly
ORG 2000H
LXI H, BLOCK
MOV B, M
INX H
MVI A, 00H
LOOP:
ADD M
INX H
DCR B
JNZ LOOP
CMA
INR A
CMP M
JZ CHKOK
MVI A, 00H
JMP WRITE
CHKOK:
MVI A, 0FFH
WRITE:
STA STATUS
END
```
3. Address Decoding for Ports of 8255
Analysis: Determine port addresses for two 8255 chips based on the decoding scheme shown in figure.
Port Addressing:
- 1st 8255 Addresses:
- Port A: 60H or 64H
- Port B: 61H or 65H
- Port C: 62H or 66H
- Control Port: 63H or 67H
- 2nd 8255 Addresses:
- Port A: E0H or E4H
- Port B: E1H or E5H
- Port C: E2H or E6H
- Control Port: E3H or E7H
4. Function of IO/M* Signal
IO/M* = 0: Memory machine cycle (Read, Write, Opcode fetch).
IO/M* = 1: I/O machine cycle (I/O Read, I/O Write).
5. Interfacing Display and Switches with 8255
Description: Show how to interface three seven-segment displays (common cathode) directly to the first 8255 port and 12 switches to the second 8255 port.
Program Code for Display:
PORTA1: EQU 60H
PORTB1: EQU 61H
PORTC1: EQU 62H
CTRLPORT1: EQU 63H
PORTA2: EQU E0H
ORG 2000H
MVI A, 80H
OUT CTRLPORT1 ; Port A,B,C – output (7-seg)
MVI A, 92H
OUT CTRLPORT2 ; Port A,B – input (switch)
IN PORTA2
MOV B, A ; 1st
ANI 00001111B ; 4 bit LSB
CALL GET_CODE
OUT PORTA1 ; display
MOV A, B
RAR
; Other code...
```
## REVIEW – DESIGN QUESTIONS 4
### 1. Traffic Light System Schematic
- **Description**: Sketch the schematic diagram showing connections interfacing with the microprocessor through its I/O port.
- **Active LOW** ports for LEDs and active HIGH for push buttons.
### 2. Program for Traffic Light Control
- **Program Flow**:
- Initialize ports, control lights based on switch conditions, and implement delays using a switch input to control the sequence of the traffic lights.
- **Example Program Code**:
assembly
PORTA: EQU 80H
PORTB: EQU 81H
PORTC: EQU 82H
CTRLPORT: EQU 83H
ORG 2000H
MVI A, 1000 0010B ; PORT C = OUTPUT, PORT B = INPUT
OUT CTRLPORT
START:
; Additional traffic light control logic…
EXIT: JMP EXIT
END
```
3. Countdown Counter for Motorists
Software Modification:
- Implement a countdown routine displayed on 7-segment displays and trigger additional outputs based on the countdown.
REVIEW – DESIGN QUESTIONS 5
1. Delay Calculation for Subroutine
Time Calculation:
- For a 15 ms software delay with a processor clock of 350 ns, calculate the value of N:
- Total T-states:
- From the subroutine, assert what operations contribute to this T-state rise.
2. Types of Data Transfer Instructions
Instructions: Overview of instructions in the data transfer group, including types, usage, and examples.
3. Types of Interrupts in 8085
Maskable Interrupts: Triggered by instructions enabling or disabling them (e.g., SIM instruction).
Example: Explanation of enabling, disabling, and masking interrupts in the processor.
REVIEW – THEORETICAL QUESTIONS 8
1. General Block Diagram of Microprocessor-Based System
Components: CPU, memory, I/O Devices, Explain examples for each block type,
2. Microprocessor Overview
Definition: What constitutes a microprocessor and its various pins.
3. Signal Diagram Explanation
Discuss 8085 signals (READY, S1 & S0, HOLD & HLDA, ALE) and their operational implications.
4. Microprocessor Architecture
Explain the architecture with diagrams outlining the register structure,
5. Memory in the System
Function and requirement of RAM and ROM in an 8085 microcomputer setup.
6. Instruction Cycles and Machine Cycles
Distinguish between instruction cycle, machine cycle, and T-states.