Comprehensive Study Notes: Digital Systems A

Course Overview and Instructional Staff

• Course Structure and Sequence:

  • Digital Systems A: First course in the sequence, conducted in Quarter 1. Covers fundamental digital theory, Boolean algebra, combinational logic, SystemVerilog hardware description, implementation technologies, and sequential logic.
  • Digital Systems B: Continuation course offered in Quarter 3, expanding on microarchitectures and advanced digital design.
  • Smart Robot Challenge: Quarter 4 project course integrating digital systems knowledge. Students program an autonomous robot to navigate a maze, avoid obstacles, and compute shortest paths using C code on a host PC communicating wirelessly with motor and sensor controllers.
  • Chip Design: Elective course offered in the second and third years covering physical integrated circuit design.
  • Master Program: Computer and Embedded Systems Engineering.

• Instructional Team and Roles:

  • Rayan Varcantara:
  • Master's degree completed in 1985; PhD completed in 1991 focusing on computer-aided design software for integrated circuits (ICs).
  • Co-lecturer for Digital Systems A and Digital Systems B.
  • Program Coordinator for the Smart Robot Challenge and Course Coordinator/Instructor for Chip Design.
  • Master Coordinator for Computer and Embedded Systems Engineering.
  • Office located on the 9th floor.
  • Mansoura:
  • PhD recipient from the Indian Institute of Technology (IIT) Delhi.
  • Co-lecturer for Digital Systems A and Digital Systems B.
  • Co-instructor for the Smart Robot Challenge, Chip Design, and Computer Architecture and Organization.
  • Tom Slatz:
  • Laboratory Director and Manager in charge of course practicals.
  • Involved in Digital Systems A and B, Smart Robot Challenge, and Computer Architecture and Organization.

Course Assessment, Schedule, and Bonus Mechanics

• Lecture and Lab Timeline:

  • Weeks 1–4: 5 lectures covering Intro, Boolean Circuits/Algebra, Logic Minimization, SystemVerilog, and Combinational Modules/Implementation Technology.
  • Course Labs: Two compulsory hands-on lab sessions held during the first four weeks, with two additional sessions in the second half of the quarter. Practicals are executed in pairs of two students. Results must be signed off by Teaching Assistants (TAs). Copying work from others is strictly flagged as academic fraud.
  • Week 4: Off-campus paper-based Trial Exam (Test 1) held in an exam hall to simulate partial exam conditions.
  • Week 5: Partial Exam 1 (covers material from Weeks 1–4).
  • Weeks 6–9: 4 lectures covering Sequential Logic, Memory Elements, and Finite State Machines (FSMs), accompanied by 4 assignment sets and 2 lab sessions.
  • Week 9: Test 2 (conducted online).
  • Re-examination: Offered in January 2027 covering the complete course material for students seeking to remediate an insufficient final grade.

• Homework & Seminars:

  • Weekly assignment sets accessible online via graspol.com following each lecture.
  • Weekly practical seminars (e.g., Fridays) dedicated to problem-solving, formula practice, and student Q&A.

• Exam Policies and Allowed Materials:

  • Open-book policy: Students may bring the textbook and printed lecture slides to the exams.
  • Note on preparation: Relying solely on searching the textbook during the exam leads to time exhaustion; core concepts and mechanisms must be thoroughly memorized and practiced prior to testing.

• Grading and Bonus System Mechanics:

  • Final Grade is calculated as the average of Partial Exam 1 (Weeks 1–4) and Partial Exam 2 (Weeks 6–9).
  • Let $R$ be the average score of the two practice tests (Test 1 and Test 2).
  • Let $T$ be the average score of the two partial exams (Partial Exam 1 and Partial Exam 2).
  • The final computed grade incorporating the test bonus formula adjusts lower partial exam scores upward. For example, an insufficient exam average of $T = 5.4$ can be scaled up to a passing grade of $5.8$ if the student scores high marks on the practice tests $R$
  • The maximum bonus yield is $0.5$ points for exam scores situated around the passing threshold ($5.4$). No bonus is added if the partial exam average $T$ is already a perfect $10.0$.

Ubiquity and Anatomy of Digital Systems

• Application Domains:

  • Embedded hardware in smartphones, video game controllers, personal computers, telecom infrastructure, home appliances, automotive electronic control units (ECUs), aerospace systems, and biomedical instrumentation.

• System Decomposition (Hardware vs. Software):

  • Hardware: Physical components, electronic components, and integrated circuits. Primary domain of Electrical Engineering.
  • Software: Code layers including operating systems (e.g., Apple iOS), application programs, user databases, compilers, and hardware device drivers (the bridge software between the operating system and physical sensors/actuators). Primary domain of Computer Science.

• Hardware Architecture of a Smartphone (iPhone 16 Case Study):

  • Major Structural Components: High-resolution display, lithium-ion battery, camera assemblies, environmental/motion sensors, audio speakers, and a taptic engine (haptic actuator generating physical touch sensations).
  • Logic Board Configuration: Consists of two double-sided Printed Circuit Boards (PCBs):
  1. RF (Radio Frequency) PCB: Manages analog radio signals including GSM cellular connectivity, 5G transceiver lines, Wi-Fi, Bluetooth, and GPS.
  2. Main Digital Logic PCB: Houses high-density digital compute silicon, system memory, power management ICs, display controllers, and audio amplifiers.
  • Apple A18 Processor Specifications:
  • Fabrication Technology Node: $3\text{ nm}$ feature size.
  • Physical Transistor Dimension: The gate dimensions are $3\text{ nm}$ wide. Given a single silicon atom diameter of approximately $0.2\text{ nm}$, transistor features span only a few tens of atoms across.
  • Die Area: $90\text{ mm}^2$
  • Transistor Count: $15,000,000,000$ ($15\text{ billion}$) transistors integrated on a single silicon die.
  • Execution Core Breakdown:
    • 5 Graphical Processing Unit (GPU) cores.
    • 6 ARM CPU cores: 2 High-Performance cores running at up to $4\text{ GHz}$ / $5\text{ GHz}$ for demanding tasks (such as video editing), and 4 Low-Performance Energy-Efficient cores for lightweight background operations.
    • Dedicated Neural Network Engines for machine learning tasks (e.g., real-time face recognition).
  • Auxiliary System ICs: Dedicated power management chips, battery charging controller ICs, display controllers, camera ICs, SIM card readers, USB interface controllers, and analog audio amplifiers.

Digital Circuit Fundamentals & Implementation

• The Transistor as a Digital Switch:

  • Transistors are three-terminal semiconductor devices used as analog amplifiers or high-speed digital switches.
  • In digital logic, applying either a low or high voltage to the transistor gate terminal toggling the device between an OFF state (logic 0) and an ON state (logic 1).

• Hierarchical Circuit Abstraction:

  • Transistors: Lowest physical abstraction layer (e.g., a 2-input NAND logic gate requires $4$ individual transistors).
  • Logic Gates: Small circuits such as NAND, NOR, NOT, AND, OR, and XOR.
  • Functional Modules: Intermediate arithmetic blocks compiled from logic gates (e.g., binary adders, multipliers, multiplexers).
  • Processors: System-level integrated circuits combining execution cores, cache memory, registers, and interconnect buses containing billions of transistors performing parallel logic operations.

• Combinational vs. Sequential Logic:

  • Combinational Logic: Output depends exclusively on the current combination of inputs. Has no memory or internal feedback storage (e.g., logic gates, adders, multiplexers).
  • Sequential Logic: Output depends on both current inputs and previous history/states. Contains memory elements (e.g., flip-flops, registers, Finite State Machines [FSMs]).

• System Design Trade-offs (Hardware vs. Software):

  • 100% Hardware Implementation: Direct gate-level silicon execution. Offers maximum processing speed, massive task parallelism, and low power consumption for specific operations, but is rigid and difficult to alter post-fabrication.
  • 100% Software Implementation: Program code executed sequentially on a general-purpose microprocessor. Offers maximum flexibility and ease of algorithm updates, but incurs lower raw execution speed and higher power consumption.
  • Hybrid Design: Implementation balancing performance and flexibility by placing critical inner-loop algorithms into dedicated hardware blocks while controlling high-level flow via microcontroller instructions stored in Read-Only Memory (ROM).

• Thermostat Controller Design Example:

  • Inputs: Measured temperature $T$, target reference temperature $T_{\text{ref}}$, and system status flag $\text{ok}$.
  • Parameter: Threshold margin $\text{delta}$ ($\text{delta} > 0$) to prevent constant high-frequency toggling.
  • Algorithmic Logic Rules:
  • Heat Mode: If $T_{\text{ref}} - T > \text{delta}$ AND $\text{ok} == \text{true}$, set $\text{heat} = \text{true}$.
  • Cool Mode: If $T_{\text{ref}} - T < -\text{delta}$ AND $\text{ok} == \text{true}$, set $\text{cool} = \text{true}$.
  • Idle Mode: If $|T_{\text{ref}} - T| \text{delta}$ OR $\text{ok} == \text{false}$, maintain system state at idle.

• Digital Design Workflow:

  1. Textual Specification: Natural language definition of system behavior.
  2. Boolean Equation: Formal mathematical definition (e.g., $\text{heat} = \text{too}\text{\_}\text{cold} \times \text{ok}$).
  3. SystemVerilog HDL: Register-Transfer Level (RTL) code description (e.g., assign heat = too_cold & ok;).
  4. Logic Simulation: Waveform testing to verify functionality against specifications.
  5. FPGA Prototyping: Synthesis and bitstream download onto hardware for validation.

• Field Programmable Gate Arrays (FPGAs):

  • Semiconductor devices containing thousands to millions of uncommitted logic gates and embedded SRAM configuration cells.
  • Logic routing is set by programming binary values into SRAM memory cells: writing a 1 creates a physical connection line, while writing a 0 disconnects it.
  • Re-programmable nature enables rapid prototyping and hardware testing without committing to expensive custom silicon manufacturing.

Digital vs. Analog Representations

• Core Definitions:

  • Analog: Continuous signal representations taking infinite possible values over a continuous range (e.g., mercury column height, continuous voltage levels, pointer position on an analog meter, mathematical constants like $\text{pi}$ or $e$).
  • Digital: Discrete representations constrained to a finite set of states or digits (e.g., digital display values, truncated numerical values such as $3.1415$, low/high binary voltage states).

• Noise Immunity Comparison (Temperature Sensing Scenario):

  • Goal: Transmit a room temperature reading across a range of $0^\text{o}\text{C}$ to $100^\text{o}\text{C}$ with a resolution of $0.1^\text{o}\text{C}$ (e.g., sending $25.0^\text{o}\text{C}$).
  • Single-Wire Analog Approach:
  • Represents temperature using a continuous voltage line from $0\text{ V}$ to $10\text{ V}$.
  • The target value $25.0^\text{o}\text{C}$ maps to $2.50\text{ V}$.
  • Required voltage measurement accuracy is $0.01\text{ V}$ ($10\text{ mV}$).
  • Vulnerability: Electrical noise inducing a minor spike of $10\text{ mV}$ ($0.01\text{ V}$) corrupts the data reading, changing $25.0^\text{o}\text{C}$ to $25.1^\text{o}\text{C}$ with no recovery possible.
  • 3-Wire 10-Level Digital Approach:
  • Represents digits using 3 dedicated lines, each supporting 10 distinct voltage steps ($0\text{ V}, 1\text{ V}, 2\text{ V}, \text{...}, 9\text{ V}$).
  • The target value $25.0^\text{o}\text{C}$ maps to integer $250$, driving wire 1 to $2\text{ V}$, wire 2 to $5\text{ V}$, and wire 3 to $0\text{ V}$.
  • Required voltage step separation is $1.0\text{ V}$.
  • Vulnerability: A noise spike causing a $2\text{ V}$ signal to drift to $2.2\text{ V}$ or $1.9\text{ V}$ is successfully rejected by threshold logic, recovering the exact digit 2 correctly.
  • Multi-Wire Binary Digital Approach:
  • Restricts every line to only 2 binary states (Low = 0, High = 1).
  • Requires additional signal wires, but yields absolute noise margins. Transistors easily distinguish between zero volts and full supply rail voltage ($1.2\text{ V}$, $3.0\text{ V}$, or $5.0\text{ V}$).

Binary Arithmetic & Boolean Operators

• Binary Digits (Bits):

  • A bit (binary digit) represents the smallest atomic unit of information in digital systems, taking a state of 0 (false / low voltage) or 1 (true / high voltage).

• Fundamental Boolean Algebra Operators:

  • NOT (Inversion): Denoted by a prime $X'$ or an overbar $\bar{X}$.
  • Truth Table: $\bar{0} = 1$, $\bar{1} = 0$
  • AND (Conjunction): Denoted by a dot $X \times Y$ or concatenated $XY$
  • Output is 1 if and only if all inputs are 1. Truth Table:
    • $0 \times 0 = 0$
    • $0 \times 1 = 0$
    • $1 \times 0 = 0$
    • $1 \times 1 = 1$
  • OR (Disjunction): Denoted by a plus sign $X + Y$
  • Output is 1 if at least one input is 1. Truth Table:
    • $0 + 0 = 0$
    • $0 + 1 = 1$
    • $1 + 0 = 1$
    • $1 + 1 = 1$

• Data Encoding Standards:

  • Characters / Text: Encoded into binary patterns. ASCII uses 8 bits ($1\text{ byte}$) per character, yielding $2^8 = 256$ unique bit configurations ($0$ to $255$).
  • Sound: Created by sampling continuous air pressure analog waveforms at defined time intervals and quantizing values into binary integers.
  • Images: Represented as two-dimensional grid matrices of pixels, where each pixel stores multi-bit binary values defining Red, Green, and Blue (RGB) intensity levels.
  • Video: Sequences of image frame matrices transmitted over time at set refresh frequencies (e.g., $50\text{ Hz}$ = 50 full binary image frames per second).

Number Base Conversions

• Positional Number Systems:

  • General positional value calculation formula for a number in base $b$ with digits $d_n \text{...} d_1 d_0$:     $\text{Value}_{10} = \text{sum}_{i=0}^{n} \text{left}( d_i \times b^i \text{right})$

• System Definitions:

  • Decimal (Base 10): Digits $\text{left}\{0, 1, 2, 3, 4, 5, 6, 7, 8, 9\text{right}\}$. Base weights are powers of 10 ($10^0, 10^1, 10^2, \text{...}$).
  • Binary (Base 2): Digits $\text{left}\{0, 1\text{right}\}$. Base weights are powers of 2 ($2^0, 2^1, 2^2, 2^3, \text{...}$).
  • Octal (Base 8): Digits $\text{left}\{0, 1, 2, 3, 4, 5, 6, 7\text{right}\}$. Base weights are powers of 8 ($8^0, 8^1, 8^2, \text{...}$).
  • Hexadecimal (Base 16): Digits $\text{left}\{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, \text{A}, \text{B}, \text{C}, \text{D}, \text{E}, \text{F}\text{right}\}$, where alpha characters represent values $\text{A}=10, \text{B}=11, \text{C}=12, \text{D}=13, \text{E}=14, \text{F}=15$. Base weights are powers of 16 ($16^0, 16^1, 16^2, \text{...}$).

• Base Conversion Demonstrations (Evaluating Value 26):

  • Decimal Representation: $26_{10} = 2 \times 10^1 + 6 \times 10^0 = 20 + 6 = 26$
  • Binary Representation: $11010_2$$\text{Value}_{10} = 1 \times 2^4 + 1 \times 2^3 + 0 \times 2^2 + 1 \times 2^1 + 0 \times 2^0 = 16 + 8 + 0 + 2 + 0 = 26$
  • Octal Representation: $32_8$$\text{Value}_{10} = 3 \times 8^1 + 2 \times 8^0 = 24 + 2 = 26$
  • Hexadecimal Representation: $1\text{A}_{16}$$\text{Value}_{10} = 1 \times 16^1 + 10 \times 16^0 = 16 + 10 = 26$

• Successive Division Algorithm (Decimal to Binary Conversion):

  • To convert decimal integer $N_{10}$ to binary, repeatedly divide the quotient by $2$ and record the integer remainder. The first remainder calculated forms the Least Significant Bit (LSB, $2^0$), and the final remainder forms the Most Significant Bit (MSB).
  • Example: Convert $26_{10}$ to Binary:
  1. $26 / 2 = 13$, remainder $0$ (LSB)
  2. $13 / 2 = 6$, remainder $1$
  3. $6 / 2 = 3$, remainder $0$
  4. $3 / 2 = 1$, remainder $1$
  5. $1 / 2 = 0$, remainder $1$ (MSB)
  • Concatenating remainders from MSB to LSB yields $11010_2$.