Computer Architecture and Organisation - Introduction

Course Overview and Assessment

  • Course Learning Outcomes (CLOs):

    • Explain the structures and functions of primary computer components.

    • Construct simple assembly language programs and programs for programmable peripheral interface devices.

    • Formulate solutions for computer architecture and organization problems as a team.

  • Assessment Structure:

    • Lab Reports: 25%25\% (Labs 44 to 88).

    • Written Test: 25%25\%

    • Group Project: 50%50\% (Report and presentation, 44 members per team).

First Generation: Vacuum Tubes (1946–1957)

  • ENIAC (Electronic Numerical Integrator And Computer):

    • Developed by John Mauchly and John Eckert at the University of Pennsylvania (1943194319461946).

    • The world’s first general-purpose electronic digital computer.

    • Characteristics: 3030 tons, 15001500 square feet, 18,00018,000 vacuum tubes, and 140kW140\,kW power consumption.

    • Capacity: 50005000 additions per second; decimal-based machine with manual programming via switches and cables.

  • IAS Computer (von Neumann Machine):

    • Proposed the stored-program concept: instructions and data are stored in the same memory.

    • Structure consists of the Central Processing Unit (CPU), Main Memory, and Input/Output (I/O) equipment.

    • IAS Memory Formats: 40964096 storage locations (words) of 40bits40\,bits each.

  • Key IAS Registers:

    • MBR (Memory Buffer Register): Contains words to be stored in or received from memory/IO.

    • MAR (Memory Address Register): Specifies the memory address for MBR operations.

    • IR (Instruction Register): Holds the 8bit8\,bit opcode being executed.

    • IBR (Instruction Buffer Register): Holds the right-hand instruction from a memory word.

    • PC (Program Counter): Contains the address of the next instruction pair.

    • AC (Accumulator) and MQ (Multiplier Quotient): Temporarily hold operands and ALU results.

  • Commercial Computers:

    • UNIVAC I: First successful commercial computer (19501950).

    • IBM 701701 (19531953): Primary scientific focus; IBM 702702 (19551955): Business applications.

Second and Third Generations

  • Second Generation: Transistors (1958–1964):

    • Smaller, cheaper, and lower heat dissipation than vacuum tubes.

    • Introduced high-level programming languages and system software.

    • Digital Equipment Corporation (DEC) introduced the PDP-1 in 19571957.

  • Third Generation: Integrated Circuits (1965–1971):

    • Based on microelectronics: gates (data processing) and memory cells (data storage).

    • Notable machines: IBM System/360360 and DEC PDP-88.

Moore’s Law and Chip Evolution

  • Moore’s Law: Observed by Gordon Moore in 19651965; states the number of transistors on a single chip doubles approximately every 1818 months.

  • Consequences: Reduced costs, increased operating speeds due to shortened electrical paths, smaller physical sizes, and reduced power/cooling requirements.

  • Later Generations:

    • LSI (Large Scale Integration).

    • VLSI (Very Large Scale Integration).

    • ULSI (Ultra Large Scale Integration).

Microprocessors and Intel x86 Evolution

  • Intel Milestones:

    • 40044004 (19711971): First CPU on a single chip (4bit4\,bit).

    • 80088008 (19721972): First 8bit8\,bit microprocessor.

    • 80808080 (19741974): First general-purpose microprocessor.

    • 80868086 (19781978): First appearance of the x86 architecture (16bit16\,bit).

    • 8038680386 (19851985): First 32bit32\,bit Intel machine; supported multitasking.

    • Pentium Series: Introduced superscalar execution (parallel instructions) and multimedia enhancements (MMX).

    • Core Series: Dual-core implementation (20062006) and transition to 64bit64\,bit architectures.

Performance Design Techniques

  • Speed Techniques:

    • Pipelining: Overlapping stages of instruction processing.

    • Branch Prediction: Predicting which instruction groups are processed next.

    • Data Flow Analysis: Optimizing schedules based on instruction dependencies.

    • Speculative Execution: Executing instructions ahead of appearance using branch prediction.

  • Performance Balance: Adjusting architecture to mitigate component mismatches, such as widening DRAM paths, using multi-level cache hierarchies, and increasing bus bandwidth.

  • Current Obstacles: Power density/heat dissipation, RC delay (resistive-capacitive limits of thin wires), and the memory latency gap relative to processor speed.