Performance Issues in Computer Organization and Architecture

Designing for Performance

  • Cost and Performance Trends

    • Computer systems are becoming less expensive while their performance and capacity increase.
    • Modern laptops can outperform older IBM mainframes (from 10-15 years ago).
    • Microprocessors are now so inexpensive that disposable microprocessors have become common.

  • Demand for Processing Power

    • Applications utilizing modern microprocessor capabilities:
    • Image processing
    • 3D rendering
    • Speech recognition
    • Videoconferencing
    • Multimedia authoring
    • Voice and video annotations
    • Simulation modeling
    • Businesses depend on powerful servers for transaction and database processing, moving away from traditional mainframe centers.
    • Cloud service providers rely on high-performance server banks for high-transaction applications.

Microprocessor Speed Enhancements

  • Techniques for Improved Performance:

    • Pipelining: Instructions processed in overlapping stages for efficiency.
    • Branch Prediction: Anticipating the next instructions from fetched code.
    • Superscalar Execution: Issuing multiple instructions per clock cycle using parallel pipelines.
    • Speculative Execution: Executing instructions ahead of their sequence based on predictions.

  • Instruction Processing:

    • Pipelining enables continuous instruction flow through overlapping sections of the processor.
    • In a Superscalar Pipeline, multiple instructions may execute simultaneously.

  • Example of Data Flow Analysis:

    • Dependencies among instructions illustrate how processor optimizes execution:
    1. ADD R1, R2, R3
    2. MUL R6, R2, R3 (can be done earlier)
    3. SUB R4, R1, R5
    4. ADD R7, R4, R6
    • Optimizing order minimizes pipeline stalls.

Speculative Execution

  • Example of Execution:
    • Using instruction like CMP AX, BX, the processor predicts outcomes and speculatively executes one path.
    • Results of speculative execution are either committed or discarded based on prediction accuracy.

Performance Balance Strategies

  • Techniques to enhance performance include:
    • Making DRAMs wider to increase retrieval capacity.
    • Efficiently incorporating caches on DRAM chips to reduce access frequency.
    • Utilizing high-speed buses to increase interconnect bandwidth.
    • Architectural adjustments to align with component capabilities.

Architectural Improvements

  • Tech Trends:

    • Increased processor speeds from reduction in logic gate size and tightly packed gates.
    • Enhanced cache size/speed with dedicated cache on chip leading to lower access times.

  • Clock Speed Limitations:

    • Increased power density, heat dissipation issues, and delays due to resistance and capacitance limits effective clock speed improvements.

Multicore and Many Integrated Core (MIC) Architecture

  • Multicore systems improve performance without increasing clock rates by using simpler processors.
  • MIGs leverage parallelism across multiple cores for better throughput in graphics and computational tasks.

Amdahl’s Law

  • Amdahl’s Law illustrates the limitations of parallelization for multi-core machines, noting that software must adapt for effective speedup.
    • Equation: extSpeedup=T(1−f)T+fTNext{Speedup} = \frac{T}{(1-f)T + \frac{fT}{N}} where:
    • f = fraction of the program that can be parallelized.
    • N = number of processors.

Little’s Law

  • Fundamental relationship related to queuing systems:
    • Describes the average number of items in a system as a function of the arrival rate and the time an item spends in the system: L=extλimesWL = ext{λ} imes W where:
    • L = average number of items in the system.
    • λ = average rate of arrivals.
    • W = average time an item spends in the system.