NVM Notes

Introduce

• Non-volatile memory (NVM) or non-volatile storage retains stored information even after power is removed, making it suitable for long-term data storage. This is crucial in applications where data must be preserved during power outages or system shutdowns.

• Volatile memory needs constant power to retain data, making it unsuitable for long-term storage. Examples include SRAM and DRAM, which are used for temporary data storage due to their speed but lose data when power is lost.

• NVM types include:

  • One Time Program (OTP): Programmable only once, typically used for storing configuration data or unique identifiers.

  • Fuse OTP: Uses fuses that are blown to program the memory cell.

  • Anti Fuse OTP: Uses dielectric breakdown to create a permanent connection.

  • Logic NVM: Implemented using standard logic gates and transistors, offering a cost-effective solution for low-density storage.

  • Multi Time Program (MTP): Can be programmed multiple times, offering more flexibility than OTP.

  • EEPROM (electrically erasable programmable ROM): Can be electrically erased and reprogrammed, typically used for storing small amounts of data that need to be updated occasionally.

  • Flash: A type of EEPROM that can be erased and programmed in blocks, offering high density and fast read speeds. There are two main types: NOR and NAND.

  • Logic NVM: Implemented using standard logic gates and transistors, offering a cost-effective solution for low-density storage.

Applications

• Applications for NVM based on customer requirements:

  • A few bits: Storing analog trim info for RF ICs; infrequently updated. These are used to calibrate analog circuits and compensate for process variations.

  • Several tens of bits: Chip IDs, serial numbers; programmed once and not changed. Essential for tracking and identifying devices.

  • Hundreds to thousands of bits: Security keys, data for RFID; programmed once and not changed. Used in authentication and access control systems.

  • Megabits of data: Code storage for microcontrollers; frequent changes may be needed. Allows for firmware updates and storing large amounts of program code.

Fuse OTP

• Bitcell and Operation:

  • Structure:

    • Read NMOS: Transistor used to read the state of the fuse.

    • Program NMOS: Transistor used to control the programming current.

    • Fuse (created by poly, metal, or via): The element that is selectively broken to store data. Materials such as polysilicon, metal, or conductive vias are used.

    • Some structures use 1 transistor and 1 fuse. The transistor is used for both read and program operations. Thicker oxide is needed to withstand the high current of programming.

- Program:

    - Apply voltage V{pp} and V{dd}, and 0. V{pp} is the programming voltage, and V{dd} is the supply voltage.

    - Large current goes through the fuse, causing electromigration. Electromigration is the mass transport of metal atoms due to the momentum transfer between conducting electrons and metal atoms.

    - The fuse changes from shorted to open. This creates a permanent change in the bitcell's resistance.

    - The current must be large enough to break the fuse. The required current depends on the fuse material and dimensions.

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- Read:

    - Apply 0, 0, and V[dd}. Applying 0V to the gate and source, and V[dd} to the drain allows for sensing the fuse state.

    - If the fuse is shorted (not programmed), current flows through the bitcell. This indicates a '0' or unprogrammed state.

    - If the fuse is open (programmed), no current flows through the bitcell. This indicates a '1' or programmed state.

    - The BL connects to the sense amplifier. The sense amplifier detects the small current difference and outputs a digital signal.

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- 1T1R Structure:

    - Some structures use 1 transistor and 1 fuse.

    - The transistor is used for both read and program operations. Thicker oxide is needed to withstand the high current during programming. The thicker oxide prevents the transistor from breaking down during programming.

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Anti Fuse OTP

• Bitcell and Operation:

  • Structure:

    • MOSCAP device (as a capacitor before programming)

    • MOSFET device

- Program:

    - Apply high voltage V{pp} (High Voltage), V{dd}, and 0

    - High voltage is applied to the Vgate of the MOSCAP device. This voltage exceeds the breakdown voltage of the oxide.

    - The oxide breaks down, and the capacitor becomes a resistor. This creates a permanent conductive path.

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- Read:

    - Apply 0, V[dd}.

    - If programmed, the MOSCAP oxide becomes a resistor, allowing current flow from BL to WWL. This indicates a '1' or programmed state.

    - If not programmed, the MOSCAP oxide remains a capacitor, and no current flows from BL to WWL. This indicates a '0' or unprogrammed state.

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- Other structures:

    - Some bitcells use only one transistor, created with two thicknesses of oxide during fabrication.

    - Thin oxide: acts like the oxide of MOSCAP. This is designed to break down during programming.

    - Thick oxide: acts like the oxide of MOSFET. This remains intact and is used for read operations.

    - During programming, the thin oxide breaks down, changing from a capacitor to a resistor.

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Flash OTP

• Bitcell and Operation:

  • Structure of bitcell:

    • Select FET: Used to select the bitcell for read or program operations.

    • Floating Gate FET: The core memory element where charge is stored.

- Operations:

    - Erase: Use UV to erase the floating-gate transistor. This step removes any charge stored on the floating gate.

    - Program: 0, V{pp}, 0, PP, V{PP},V[PP}

    - Read: 0, V{dd}, Sense, V{dd}

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- Erase Operation:

    - The floating-gate transistor can be erased coming out of the fab by a UV erase step.

    - After erased, there is no charge on the floating gate. This sets the initial state of the memory cell.

    - If we do the read in erased cell, consider the FG FET:

        - V{bulk} = V{dd}

        - V{source} = V{dd}

        - V{gate} = V{dd}

        - FG FET is off

        - There is no current in BL to Sense amp

        - NW: V[dd}

        - Neutral charge

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- Program Operation:

    - During programming, the floating gate is at high voltage and injects electrons into the gate.

    - The floating gate now charges negatively. This increases the threshold voltage of the transistor.

    - If we do the read in programmed cell, consider the FG FET:

        - V{bulk} = V{dd}

        - V{source} = V{dd}

        - V{gate} = lower than V{dd}

        - FG FET is on

        - There is current in BL to Sense amp

        - NW: V[dd}

        - Negative charge

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Supper Flash SST

• Bitcell and Operation:

  • SuperFlash is a type of NOR Flash memory that uses a split-gate cell architecture. This architecture improves performance and reliability.

  • Provides superior performance, data retention, and reliability over conventional stacked gate Flash.

  • The floating gate is both a charge storage element and a read-sensing element. This simplifies the cell structure and improves performance.

  • Charge on the floating gate affects the (apparent) threshold of the memory element.

    • Floating gate neutral: low V[th}

    • Floating gate charge negative: high V[th}

- Read Operation:

    - Cell erased: neutral floating gate → low V[th} → large current

    - Cell programmed: negative floating gate → high V_t → no current

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- Program Operation:

    - The current goes through the channel.

    - Electrons go into the Floating gate by effect of HCI (Hot Carrier Injection).

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- HCI (Hot Carrier Injection):

    - The carrier is injected from the conducting channel in the silicon substrate to the gate dielectric SiO_2. This is a key mechanism for programming the memory cell.

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- Erase Operation:

    - Apply high voltage to the WL.

    - Electrons go out of the Floating gate by effect of Fowler-Nordheim Tunneling. High voltage (12V) used.

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