Comprehensive Study Guide on Flip-Flops and Sequential Logic

Introduction to Logic Circuits

  • In digital systems, logic circuits are categorized into two primary groups:
    • Combinational logic circuit: The output signal value at any given time is determined strictly by the values of the input signals at that time. These circuits are constructed using AND, OR, and NOT gates.
    • Sequential logic circuit: The output signal value at any time is determined by the values of the current input signals and the previous sequence of inputs to the circuit. These circuits involve timing and memory devices and deal with concepts such as next state, present state, and present input state.
  • General Block Diagram for a Sequential Circuit:
    • It consists of a combinational circuit and memory elements.
    • Memory Element: A device capable of storing binary information, required in most digital systems. A flip-flop is a primary example.
    • The diagram flow is: Input →\rightarrow Combinational circuit →\rightarrow Output; with a feedback loop where the combinational circuit feeds into the memory element, and the memory element feeds back into the combinational circuit.

Flip-Flops Overview

  • Definition: A flip-flop is a type of bistable memory element, meaning it has two stable states. It is considered a basic form of memory.
  • Outputs: A flip-flop typically has two outputs labeled as QQ (normal) and Q′Q' (complementary). Under normal conditions, these two outputs are the inverse of each other.
  • Latch: One use of a flip-flop is to hold or "latch" data. When used for this purpose, it is specifically called a latch. A latch can hold one bit of information.
  • Applications of Flip-Flops:
    • Counters
    • Shift registers
    • Delay units
    • Frequency dividers
  • Primary Types of Flip-Flops (FF):
    • The S-R Flip-Flop
    • The Clocked R-S Flip-Flop
    • The D Flip-Flop
    • The J-K Flip-Flop

The S-R Flip-Flop (Set-Reset)

  • The S-R Flip-Flop (or R-S Latch) can be formed using cross-coupled gates in two ways:
    • Active HIGH FF: Created using cross-coupled NOR gates.
    • Active LOW FF: Created using cross-coupled NAND gates.
  • Inputs: SS (Set) and RR (Reset).
  • NAND Gate S-R Flip-Flop (Active LOW) Operation:
    • Prohibited State: When S=0S=0 and R=0R=0, both outputs go to logical 11. This state is prohibited and should not be used.
    • Set Condition: When S=0S=0 and R=1R=1, the output QQ is set to logical 11.
    • Reset Condition: When S=1S=1 and R=0R=0, the output QQ is reset (cleared) to 00.
    • Hold Condition: When S=1S=1 and R=1R=1, this is the idle/at-rest condition. Both outputs (QQ and Q′Q') remain in their previous state.
  • NAND Gate Truth Table Summary:
    • Prohibited: S=0,R=0→Q=1,Q′=1S=0, R=0 \rightarrow Q=1, Q'=1
    • Set: S=0,R=1→Q=1,Q′=0S=0, R=1 \rightarrow Q=1, Q'=0
    • Reset: S=1,R=0→Q=0,Q′=1S=1, R=0 \rightarrow Q=0, Q'=1
    • Hold: S=1,R=1→Q=Previous,Q′=PreviousS=1, R=1 \rightarrow Q=\text{Previous}, Q'=\text{Previous}
  • NOR Gate S-R Flip-Flop (Active HIGH) Operation:
    • Hold Condition: When S=0S=0 and R=0R=0, outputs follow the previous condition.
    • Reset Condition: When S=0S=0 and R=1R=1, output QQ is set to logical 00.
    • Set Condition: When S=1S=1 and R=0R=0, output QQ is set to logical 11.
    • Prohibited State: When S=1S=1 and R=1R=1, both outputs go to 00. This is prohibited and not used.
  • NOR Gate Truth Table Summary:
    • Hold: S=0,R=0→Q=Previous,Q′=PreviousS=0, R=0 \rightarrow Q=\text{Previous}, Q'=\text{Previous}
    • Reset: S=0,R=1→Q=0,Q′=1S=0, R=1 \rightarrow Q=0, Q'=1
    • Set: S=1,R=0→Q=1,Q′=0S=1, R=0 \rightarrow Q=1, Q'=0
    • Prohibited: S=1,R=1→Q=0,Q′=0S=1, R=1 \rightarrow Q=0, Q'=0

The Clocked R-S Flip-Flop

  • Features: This flip-flop includes an extra input labeled CLKCLK (clock).
  • Synchronous Operation: The outputs change only on a clock pulse. This means it operates in step with the clock, which is essential for calculators and computers where exact ordering of steps is required.
  • Memory Characteristic: Once it is SET or RESET, it remains in that state even if inputs change, provided it is in hold mode.
  • Logic Symbol: Contains inputs S,R,S, R,, and CLKCLK, with outputs QQ and Q′Q'. In the symbol, Active HIGH inputs do not have bubbles.
  • Operation Details:
    • Clock pulse 11: Inputs S=0,R=0S=0, R=0. FF is in hold/idle mode; no effect on QQ.
    • Rising edge of Clock pulse 22: Input SS moved to 11; QQ goes to 11.
    • Clock pulse 33: FF remains in set mode.
    • Clock pulse 44: FF in hold mode.
    • Rising edge of Clock pulse 55: Input RR is pre-set to 11; QQ is reset to 00. FF is in reset mode during pulses 55 and 66.
    • Clock pulse 77: Hold mode; QQ remains at 00.
  • Truth Table:
    • Hold: CLK=Pulse,S=0,R=0→No changeCLK=\text{Pulse}, S=0, R=0 \rightarrow \text{No change}
    • Reset: CLK=Pulse,S=0,R=1→Q=0,Q′=1CLK=\text{Pulse}, S=0, R=1 \rightarrow Q=0, Q'=1
    • Set: CLK=Pulse,S=1,R=0→Q=1,Q′=0CLK=\text{Pulse}, S=1, R=0 \rightarrow Q=1, Q'=0
    • Prohibited: CLK=Pulse,S=1,R=1→Q=1,Q′=1CLK=\text{Pulse}, S=1, R=1 \rightarrow Q=1, Q'=1
  • Construction: Can be wired using four NAND gates (two added to the standard R-S flip-flop to implement the clock feature).

The D Flip-Flop

  • Terminology: Known as the "delay" flip-flop, "data" flip-flop, or D-type latch.
  • Inputs/Outputs: One data input (DD) and one clock input (CLKCLK). Outputs are QQ and Q′Q'.
  • Function: The word "delay" describes the behavior where data at input DD is delayed by one clock pulse before reaching output QQ. Qn+1Q_{n+1} (the next state) follows input DD.
  • Truth Table:
    • Input D=0→Output Qn+1=0D=0 \rightarrow \text{Output } Q_{n+1}=0
    • Input D=1→Output Qn+1=1D=1 \rightarrow \text{Output } Q_{n+1}=1
  • Applications: Wired together to form shift registers and storage registers used in digital systems.
  • Internal Construction: Can be formed from a clocked R-S flip-flop by adding an inverter between the SS and RR inputs.

The Commercial 7474 TTL D Flip-Flop

  • Additional Inputs:
    • Asynchronous Preset (PS/PRPS/PR): Sets output QQ to 11 when enabled by a logical 00.
    • Asynchronous Clear (CLRCLR): Clears output QQ to 00 when enabled by a logical 00.
  • Asynchronous vs. Synchronous:
    • The PSPS and CLRCLR inputs are asynchronous; they override the synchronous DD and CLKCLK inputs.
    • "X" in the truth table represents an "Irrelevant" input.
    • "↑\uparrow" represents a LOW-to-HIGH transition (rising edge) of the clock pulse.
  • 7474 Truth Table:
    • Asynchronous Set: PS=0,CLR=1,CLK=X,D=X→Q=1,Q′=0PS=0, CLR=1, CLK=X, D=X \rightarrow Q=1, Q'=0
    • Asynchronous Reset: PS=1,CLR=0,CLK=X,D=X→Q=0,Q′=1PS=1, CLR=0, CLK=X, D=X \rightarrow Q=0, Q'=1
    • Prohibited: PS=0,CLR=0,CLK=X,D=X→Q=1,Q′=1PS=0, CLR=0, CLK=X, D=X \rightarrow Q=1, Q'=1
    • Synchronous Set: PS=1,CLR=1,CLK=↑,D=1→Q=1,Q′=0PS=1, CLR=1, CLK=\uparrow, D=1 \rightarrow Q=1, Q'=0
    • Synchronous Reset: PS=1,CLR=1,CLK=↑,D=0→Q=0,Q′=1PS=1, CLR=1, CLK=\uparrow, D=0 \rightarrow Q=0, Q'=1

The J-K Flip-Flop

  • Overview: The "universal" flip-flop because it possesses features of all other types.
  • Unique Feature: Toggle Operation. When both JJ and KK are at 11, repeated clock pulses cause the output to switch back and forth (off-on-off-on), similar to a toggle switch. This is useful for designing counters.
  • T Flip-Flop: A J-K flip-flop wired to function only in toggle mode.
  • Truth Table:
    • Hold: J=0,K=0→No changeJ=0, K=0 \rightarrow \text{No change}
    • Reset: J=0,K=1→Q=0,Q′=1J=0, K=1 \rightarrow Q=0, Q'=1
    • Set: J=1,K=0→Q=1,Q′=0J=1, K=0 \rightarrow Q=1, Q'=0
    • Toggle: J=1,K=1→Changes to opposite stateJ=1, K=1 \rightarrow \text{Changes to opposite state}

The Commercial 7476 TTL J-K Flip-Flop

  • Inputs: Includes synchronous inputs (J,K,CLKJ, K, CLK) and asynchronous inputs (PR/PSPR/PS - Preset, CLRCLR - Clear).
  • Clock Transition: Specifically uses the HIGH-to-LOW transition ("↓\downarrow") of the clock pulse to transfer data.
  • 7476 Truth Table:
    • Asynchronous Set: PS=0,CLR=1,CLK=X,J=X,K=X→Q=1,Q′=0PS=0, CLR=1, CLK=X, J=X, K=X \rightarrow Q=1, Q'=0
    • Asynchronous Reset: PS=1,CLR=0,CLK=X,J=X,K=X→Q=0,Q′=1PS=1, CLR=0, CLK=X, J=X, K=X \rightarrow Q=0, Q'=1
    • Prohibited: PS=0,CLR=0,CLK=X,J=X,K=X→Q=1,Q′=1PS=0, CLR=0, CLK=X, J=X, K=X \rightarrow Q=1, Q'=1
    • Hold (Synchronous): PS=1,CLR=1,CLK=↓,J=0,K=0→No changePS=1, CLR=1, CLK=\downarrow, J=0, K=0 \rightarrow \text{No change}
    • Reset (Synchronous): PS=1,CLR=1,CLK=↓,J=0,K=1→Q=0,Q′=1PS=1, CLR=1, CLK=\downarrow, J=0, K=1 \rightarrow Q=0, Q'=1
    • Set (Synchronous): PS=1,CLR=1,CLK=↓,J=1,K=0→Q=1,Q′=0PS=1, CLR=1, CLK=\downarrow, J=1, K=0 \rightarrow Q=1, Q'=0
    • Toggle (Synchronous): PS=1,CLR=1,CLK=↓,J=1,K=1→No change (Note: refers to state change toggle)PS=1, CLR=1, CLK=\downarrow, J=1, K=1 \rightarrow \text{No change (Note: refers to state change toggle)}

IC Latches

  • Definition: A digital storage device used as a temporary buffer memory to hold data, such as a BCD code for a decimal number on a display.
  • Examples of IC Latches:
    • CMOS: 4042,4099,74HC75,74HC3734042, 4099, 74HC75, 74HC373.
    • Combined ICs: 45114511 and 45434543 (BCD-to-seven segment latch/decoder/driver chips).
  • The Commercial 7475 4-bit Transparent Latch:
    • Contains four D flip-flops in one package.
    • Enable Input (EE): Similar to a clock. E0−1E_{0-1} controls flip-flops 00 and 11; E2−3E_{2-3} controls flip-flops 22 and 33.
    • Transparency: When the Enable input is HIGH (11), the output follows the data at the DD input immediately without a separate clock pulse.
    • Latching: When the Enable input drops to LOW (00), the IC enters data-latched mode. The state at QQ remains the same even if the DD input changes.
  • 7475 Truth Table:
    • Data Enabled: E=1,D=1→Q=1,Q′=0E=1, D=1 \rightarrow Q=1, Q'=0
    • Data Enabled: E=1,D=0→Q=0,Q′=1E=1, D=0 \rightarrow Q=0, Q'=1
    • Data Latched: E=0,D=X→Q=q0,Q′=q0′E=0, D=X \rightarrow Q=q_0, Q'=q'_0 (Previous state)