Notes 2: DATA PROCESSING
INTRODUCTION TO DATA PROCESSING IN ARM
CPU Instructions
The CPU retrieves instructions from the computer’s memory.
Each instruction is represented as a binary pattern, known as an opcode.
Assembly language was developed to create a human-readable form of machine code.
The Assembler is a tool used to convert assembly code into the corresponding bit patterns.
EXAMPLE PROGRAM
The following example illustrates an assembly program snippet:
B mainnum DEFW 5success DEFB "R0 has reached the value of ", 0ALIGNmain LDR R1, numMOV R0, #1next ADD R0, R0, #1CMP R0, R1BNE nextADRL R0, successSWI 3MOV R0, R1SWI 4MOV R0, #10SWI 0SWI 2Explanation:
The
DEFWdirective defines a 32-bit integer with a value of 5 within the bitstream.The
DEFBdirective defines a string, which is null-terminated (indicated by the trailing0).The program increments
R0until it reaches the value specified innumthen prints a success message.
MEMORY IN ARM
Memory Structure
Modern computer systems organize memory in a series of sequential bytes.
Each byte is assigned a unique identifier known as an address, starting from zero.
Instructions and data are stored in memory sequentially as determined by the assembler.
ARM provides specific instructions for accessing memory values, which can be treated as individual bytes or as a 'word'.
Word Definition: In ARM architecture, a word is defined as a 32-bit value or four consecutive bytes.
PROGRAM STRUCTURE AND DEMONSTRATION
The structure and functionality of the following memory layout can be noted:
B mainnum DEFW 5success DEFB "R0 has reached the value of ", 0ALIGNmain LDR R1, numMOV R0, #1next ADD R0, R0, #1CMP R0, R1BNE nextADRL R0, successSWI 3MOV R0, R1SWI 4MOV R0, #10SWI 0SWI 2Memory Addresses:
0:
01:
42:
83:
124:
16… (Continues every 4 bytes up to 56)
LDR INSTRUCTION
LDR Instruction
Mnemonic: LDR
Operands: Two operands are used:
A register
An address
Functionality: This instruction loads a 32-bit value from the specified address into the designated register.
It should not be confused with
ADRLwhich relates to loading addresses rather than values.An alternate version is
LDRB, which loads an 8-bit byte.
LOAD/STORE ARCHITECTURE
Architectural Design
ARM is classified as a load/store architecture CPU, which means:
Memory operations are restricted to loading (LDR) and storing (STR) only.
Other CPUs may allow more instructions to access memory.
ARM differentiates data processing instructions from memory access instructions, distinguishing itself from architectures like 68000 or x86.
STR INSTRUCTION
STR Instruction
Mnemonic: STR
Operands: Two operands:
A register
An address
Functionality: It stores a 32-bit value from the register to the specified address in memory.
It can also be suffixed to form
STRB, which handles 8-bit bytes.Both
LDRandSTRcan use an address held in a register.
DATA PROCESSING INSTRUCTIONS
General Characteristics
Operate exclusively on registers and include several mathematical and logical operations.
Can take either two or three operands, commonly formatted as:
Destination register followed by one or two source registers.
The last source register may include an immediate value (a constant number).
Instruction Format Example:
ADD Rd, Rn, Op2Rd: Destination registerRn: First source registerOp2: Second operand can be an immediate value or another register.
Additional Instruction Examples:
SUB Rd, Rn, Op2: Subtract operation.ORR Rd, Rn, Op2: Logical OR operation.
CONDITIONAL BRANCH INSTRUCTIONS
Definition
Conditional branches are noted with additional suffix letters (e.g., BNE - Branch if Not Equal).
These instructions will only execute if specified conditions are true based on flag status.
Condition Flags
Condition is determined by the state of flags stored in the Current Program Status Register (CPSR).
Not all registers affect flags; specific instructions need an 'S' suffix to modify the CPSR based on results.
CPSR Flags:
N: Negative flag, set if the last operation yielded a negative result.Z: Zero flag, set if the last operation yielded zero.V: Overflow flag, set if an overflow occurred in signed operations.C: Carry flag, set if the last operation generated a carry.
EXAMPLE OF FLAGS USAGE
Conditional Execution Demonstration:
MOVS R0, #0Sets the Z flag (zero)
BEQ fooBranches if R0 equals zero.
ADDS R0, R0, #1Updates flags based on the new value.
BMI fooBranches if R0 is negative.
MULTIPLICATION IN ARM
MUL Instruction
Mnemonic: MUL
Operands: Three operands needed - a destination and two source registers.
It cannot multiply with an immediate value.
This instruction outputs the product of the two source registers into the destination.
Suffixing this instruction with an 'S' affects the CPSR flags, indicating the result.
MLA Instruction:
Mnemonic stands for Multiply and Add.
Takes four operands: Destination, two multiplicands, and an addend register.
IMMEDIATE VALUES AND LITERAL POOLS
Encoding Immediate Values
Each instruction is a fixed 32-bits; of this, only 12-bits are available for immediate values.
Immediate values are encoded using an 8-bit part combined with a 4-bit rotation.
The assembler helps compute these rotations automatically.
LITERAL POOLS
Can utilize the LDR instruction to load values directly from memory, often through literal pools which store constant values for use in registers.
Example:
LDR R0, =0x1234578loads a constant value into R0.
FINAL EXAMPLES AND DISCUSSION
Program highlight
B mainBegins the main routine.
Implements several assembly statements above, showcasing the function of conditional branches and data processing instructions.
This comprehensive study guide provides insight into assembly programming focusing on the ARM architecture, covering the essential elements such as instruction types, conditional branches, memory structures, and more.