ECE 1004: Sequential Logic Lecture Notes

Sequential Logic in ECE 1004 - Lecture 29 Notes

Overview of Today’s Lecture

  • Subject: Sequential Logic

  • Chapter: 7 Section 6

  • Topics covered:

    • Sequential logic

    • SR latches

    • D flip-flops

  • Important Reminders:

    • Read Section 7.6

    • Lab 3 Due Tonight

    • Quiz Following Lecture

Computer Programming Hierarchy

  • Programming Languages:

    • High-Level Languages (Example): C, C++, JAVA

    • Code Example: C = A + B;

    • Assembly Language Example: ADD A, B

    • Machine Language: Binary representation such as 100100111

  • Hierarchy Summary: Shows the relationship between high-level languages and the hardware they correspond to.

Logic Fundamentals

Logic Types:

  • Combinational Logic:

    • Characteristics: No memory, output strictly based on present input.

    • Summary of Past Learning.

  • Sequential Logic:

    • Characteristics: Incorporates memory, output depends on both past and present inputs.

    • Focus of Today’s Lecture.

  • Practical digital systems utilize both combinational and sequential logic for complex operations.

Register-Transfer Level Design (RTL)

  • Definition: Abstract representation of digital circuits.

  • Important Aspects:

    • Combines both combinational and sequential logic to represent any circuit.

    • Two Main Languages: Verilog and VHDL.

    • Usage highlighted in ECE2544 with Intel’s Quartus Prime software for FPGA programming – gates are coded, synthesized to create circuits that form the core of computing devices.

Von Neumann Computer Organization

  • Components:

    • Arithmetic Logic Unit (ALU) employs combinational logic (AND, OR, NOT).

    • Memory inclusion enables sequential logic (e.g., Flip Flops).

  • This structure exemplifies modern CPU organization.

Finite State Machines (FSM)

  • Definition: Constructed using sequential logic; critical to understanding the concept of state.

  • Important Aspects:

    • Output state influenced by various external inputs.

    • State Transition: Mechanics of changing from one state to another labeled as "transition."

    • FSM memory constraints based upon the number of states available.

Simple FSM Example

  • Scenario: Coin operation with two states - Locked/Unlocked.

  • Sequential Logic Circuits verify FSM implementation.

Relating FSM to Logic Circuits

  • Components of a Simple FSM:

    • Current State

    • Next State

    • Inputs affecting transitions.

  • Data Representation: Includes Circuit Diagrams, State Tables, and State Diagrams.

Designing Robots as FSMs

  • Break tasks into manageable FSMs such as:

    • Moving forward

    • Obstacle detection

    • Turning maneuvers

    • Arm manipulations

  • Mention of the 2022 IEEE Robotics team and their successful design.

Memory Cells

  • Characteristics:

    • Basic building block of sequential circuits.

    • Possess two stable states, capable of storing 1 bit of information.

    • Variations exist, typically referred to as "latches" and "flip-flops."

    • Construction of a basic latch includes two inverters connected back-to-back.

Memory Cell as a Simple Latch

  • Functionality:

    • State definition: Q high leads to Q low and vice versa.

    • Functionality is limited due to lack of state control inputs.

Set-Reset Latch (SR Latch)

  • Enhanced memory element introducing control inputs using NOR gates.

    • Constructs useful storage elements by preventing simultaneous high conditions on S and R inputs.

  • Functionality:

    • Definition: S sets Q high; R resets Q low.

    • Memory state maintained until inputs change, allowing for retention of the last state.

  • Truth Table Reference: Represents various input-output relationships.

Real-World Applications of SR Latch

  • Example: Debouncing a switch to manage activations.

    • Mechanical systems introduce inconsistencies in state transitions (e.g., switches).

    • Observations on actual waveform behavior demonstrating switch bounce.

Example of Switch Bounce

  • Graphical Data Display: Comparison of states against time.

    • Illustrates issues in switch functionality.

Debouncing with SR Latch

  • Circuit Arrangement:

    • Includes a pull-down resistor ensuring consistent logic levels when the switch is open.

    • Waveforms illustrate how the circuit corrects switch bounces.

Clocked SR Latch

  • Implements synchronization by limiting state changes to high clock conditions.

  • Behavior: Change allowed solely when the clock signal is high.

Clocked SR with Preset and Clear

  • Functionality:

    • If preset is high, output remains high independent of the clock state.

    • Preset and Clear inputs are asynchronous and independent of the clock signal.

D Flip-Flops Overview

  • Definition: Different from SR latches, which are level-triggered.

  • Characteristic:

    • Flip-flops react on the clock’s edge rather than its level.

    • Positive-edge-triggered: Clock transitions from 0 to 1.

    • Negative-edge-triggered: Clock transitions from 1 to 0.

    • Example: Delay flip-flop also known as D flip-flop (leading edge).

Importance of D Flip-Flops

  • Widely used in applications due to precise timing and synchronization benefits.

  • They prevent concurrent S and R high conditions present in basic clocked SR latches.

Positive-Edge-Triggered D Flip-Flop Example

  • Illustrated through block diagrams and truth tables showing transition behavior.

Summary of Key Concepts

  • Latches retain set states until reset; clocked latches can change state when clocked high.

  • Flip-flops alter their state only in response to clock transitions, either positive or negative edges.

  • Emphasis on understanding the differences between D flip-flops and latches, especially in timed applications.