DDCO-Module3-notes

Module 3: Basic Structure of Computers

Functional Units

A computer consists of five functionally independent main parts that work together cohesively:

  1. Input Unit

    • Accepts information in the form of programs and data through various input devices, such as keyboards, mice, and scanners.

    • Key presses or device signals are translated into binary codes, which are then transmitted to memory or the processor for further processing.

    • Input units may also utilize touch screens or voice recognition technology, enhancing user interaction.

  2. Memory Unit

    • Stores programs and data vital for computer operations. Memory is classified into two main types:

      • Primary Storage: This includes volatile memory such as RAM (Random Access Memory), which provides fast access to data and is used to store programs during execution.

      • Secondary Storage: This includes non-volatile storage solutions like hard drives, solid-state drives, magnetic disks, and CDs, used for storing large datasets and programs long-term.

    • Memory consists of semiconductor storage cells (flip-flops) capable of storing one bit. The effectiveness of memory retrieval and organization is crucial for access times, which are fixed after the memory address is specified.

  3. Arithmetic & Logic Unit (ALU)

    • Performs fundamental arithmetic and logical operations essential for processing tasks.

    • Operands used in calculations are stored in registers within the processor, where various operations take place, including addition, subtraction, logical operations, and comparisons.

  4. Output Unit

    • Sends processed results from the computer to external devices for presentation and use, including printers, monitors, and speakers.

    • Output quality and speed can vary based on device capabilities and the data being processed.

  5. Control Unit

    • Manages and coordinates the activities of the other units (memory, input/output devices).

    • Sends control signals (e.g., read/write operations) and ensures timely data transfers through precise timing signals, orchestrating the execution of all instructions.

Basic Operational Concepts

The processor includes essential components such as:

  • ALU: Handles all arithmetic and logic tasks.

  • Control circuitry: Directs the flow of data between components.

  • Registers: Small storage locations that facilitate quick data access.

Key registers include:

  • Instruction Register (IR): Holds the instruction currently being executed.

  • Program Counter (PC): Stores the address of the next instruction to be executed.

  • General-purpose registers (R0 to Rn-1): Used for temporary data storage during instruction execution.

  • Memory Address Register (MAR): Holds memory addresses for access.

  • Memory Data Register (MDR): Stores data being read from or written to memory.

Instruction execution follows a systematic process:

  1. The first instruction address is loaded into the PC.

  2. Contents of the PC are transferred to the MAR, which then issues a Read signal to memory.

  3. The fetched instruction is stored in the MDR before being transferred to the IR for decoding.

  4. Operands are fetched into the ALU as needed, and results may be written back to memory.

Bus Structure

A bus acts as a connecting path for multiple devices, utilizing three essential lines for:

  • Data Transfer: Moving data between components.

  • Addressing: Identifying source and destination for data transfer.

  • Control Signals: Managing the timing and coordination of data flows.

Only two units can actively use the bus simultaneously, with bus arbitration determining control access.

  • Single Bus Advantage: Offers low cost and flexibility in peripheral attachment.

  • Multiple Buses: Allow for concurrent data transfers enhancing performance but at an increased cost.

Synchronization issues are addressed with buffer registers to accommodate speed differences between devices.

Processor Clock

Operations within the processor are governed by a timing signal known as a clock.

  • Clock cycles define regular execution intervals for machine instructions, dividing instructions into manageable steps.

  • The relationship between cycle length (P) and clock rate (R) is defined by the formula R = 1/P (measured in Hertz, Hz).

Basic Performance Equation

Performance metrics are defined with these variables:

  • T: Time required for program execution.

  • N: Number of executed instructions.

  • S: Average steps per instruction.

  • R: Clock rate (cycles per second).



The Program Execution Time Equation is:T = NS/RStrategies for enhancing performance involve reducing T, N, and S while increasing R, while carefully considering interdependencies among these factors.

Clock Rate

Increasing the clock rate can be achieved through two approaches:

  • Improving Integrated Circuit (IC) Technology: Reduces the time required for each basic step (lowering P).

  • Reducing Processing Steps: While this may potentially increase the overall number of steps required, it optimizes efficiency.

Performance Measurement

SPEC (System Performance Evaluation Corporation) provides standardized ratings from benchmark tests, which offer a comparative speed rating against reference computers. The overall SPEC rating is calculated as the geometric mean of the individual program ratings, giving insight into system performance metrics.

Memory and Instructions

Memory is structured with millions of storage cells (flip-flops), enabling the storage of binary data (0s and 1s).

  • Bits are grouped into words of varying lengths (common sizes are 8 to 64 bits), with bytes being the standard unit of digital information (1 byte = 8 bits).

  • Memory locations need to possess distinct addresses, ranging from 0 to 2^k-1 for k-bit addresses.

BYTE Addressability

In systems with byte addressability, each byte is assigned a unique address (0, 1, 2,...). For a memory structure where a word is 32-bits, subsequent words start at addresses that are multiples of 4.

  • Big-Endian vs. Little-Endian Assignments: In big-endian systems, more significant bytes are stored at lower memory addresses, while little-endian assignments store less significant bytes at lower addresses.

Word Alignment

Aligned words must occupy memory addresses which are multiples of their word size (e.g., 16-bit words must start at addresses 0, 2, 4).

  • Access operations for numbers and characters utilize determined word and byte addresses for efficient data manipulation.

  • Strings can be accessed either via specified lengths or control characters that indicate termination.

Memory Operations

Memory operations are fundamentally categorized into two types:

  1. Load (Read/Fetch): Transfers data from memory to the processor while preserving the original memory contents.

  2. Store (Write): Updates memory by writing the data from a processor register (like the MDR) to the specified memory location, replacing existing data.

Instruction Categories and Sequencing

Computers handle operations classified into various categories:

  • Data Transfers (e.g., MOV, PUSH)

  • Arithmetic and Logic Operations (e.g., ADD, SUB)

  • Program Control (e.g., CALL, RET)

  • I/O Transfers (e.g., IN, OUT)

Register Transfer Notation (RTN) is employed to represent operations involving memory and registers clearly and succinctly.

Assembly Language Notation

Assembly language serves as a simplified representation of machine-level instructions. Instruction types include:

  • Three-Address: For example, Add A, B, C combines values from A and B, storing the result in C.

  • Two-Address: For example, Add A, B designates B as the destination of the result.

  • One-Address: Utilizes only one operand, relying on an accumulator for results.

  • Zero-Address: Operands are accessed implicitly through the stack structure, enhancing automation of operations.

Instruction Execution and Sequencing

Instruction execution comprises the following critical phases:

  1. Fetch Phase: The first instruction is fetched using the address stored in the PC.

  2. Execute Phase: Based on the contents of the IR, the operation is determined and executed accordingly. Each execution phase increments the PC to point to the next instruction to ensure systematic processing.

Branching and Condition Codes

In scenarios requiring operations on a list of n numbers, loop constructs allow for structured processing. Branch instructions are vital during conditional executions and modify the PC based on operation flags.

  • Condition Codes: Track results of arithmetic and logical operations using flags stored in the condition code register, which include:

    • N (Negative)

    • Z (Zero)

    • V (Overflow)

    • C (Carry)

Addressing Modes

Multiple methods of operand location are classified as addressing modes, crucial for effective data manipulation:

  • Register Mode: Operand sourced directly from a specified register.

  • Absolute Mode: Operand obtained from a defined memory location.

  • Immediate Mode: Operand included directly in the instruction itself.

  • Indirect Mode: Operand retrieved indirectly using pointers to access memory addresses.

Indirection & Pointers

Registers may also function as pointers, facilitating indirect retrieval of operand values. Initialization typically involves loading counter and data addresses into registers, enabling efficient looping structures for data fetching and manipulation.

Indexing & Arrays

Indexing Mode offers enhanced flexibility in accessing lists or arrays through constant offsets associated with registers.

  • Base with Index Mode utilizes multiple registers to access operands, which is particularly useful in structured data arrangements.

  • Relative Mode determines effective addresses based on the program counter, frequently applied in branching operations.

Additional Addressing Modes

Increment and decrement addressing modes take advantage of pointers to facilitate sequential operations within lists. These addressing modes also support stack structures, crucial for efficient program organization and execution.