Introduction to Hardware Description Language (HDL)

Introduction to HDL

  • Definition: Hardware Description Language (HDL) is a class of programming languages used to describe the operation and design of electronic circuits, particularly digital logic.

  • Purpose:

  • Describe circuit operations and organizations.

  • Verify operations through simulation.

  • Types of HDLs: Common examples include Verilog, VHDL, and SystemC.

Overview and History

  • HDLs provide executable specifications for hardware design, enabling:
  • Simulations that incorporate the progression of time.
  • Modeling hardware before physical production.

Levels of Modeling

  1. Behavioral Level Modeling:
  • High-level abstraction focusing on the behavior of circuits without delving into physical implementation.
  • Easiest for designers, provides high simulation capability.
  1. Register Transfer Level (RTL) Modeling:
  • Details data transfers between registers in a circuit.
  • Commonly used for smaller sub-modules.
  1. Structural/Gate Level Modeling:
  • Represents circuit using logical gates and their interconnections.
  • Provides low-level view, often generated by synthesis tools.
  1. Transistor/Physical Level:
  • A physical representation of the design that includes transistor-level details.
  • Typically generated by tools from higher-level representations.

HDL Language Elements

  • Logic Gates: Fundamental building blocks (AND, OR, NOT, etc.).

  • Data Types: Include wire, reg, integer, real, and more. Essential for defining how data is represented and manipulated.

  • Timing and Delay: Critical for simulating how circuits will behave over time.

Language Support

  • Common HDLs:

  • Verilog: Introduced in 1984, became standardized in 1995. C-like syntax but with unique design philosophies.

  • VHDL: Similar to ADA programming language - more verbose than Verilog.

  • SystemVerilog: An extension of Verilog providing additional features for verification and design.

  • Other HDLs: Include ABEL, AHDL (Altera HDL), Bluespec, MyHDL, among others.

Hierarchical Design Methodology

  • Top-Down Design:

  • Define the high-level block and break it down into sub-blocks.

  • Continue subdividing until reaching the lowest level (leaf cells).

  • Bottom-Up Design:

  • Start with available building blocks, combine to make larger designs.

  • Assemble these into sub-blocks up to the top-level block design.

Example: 16-bit Adder

  • Hierarchical structure:
  • Design includes multiple 4-bit adders within a single 16-bit adder module.
  • Instances of full and half adders are used to build the structure.

Encapsulation in Modules

  • A module is the fundamental building block in Verilog respective to classes in C++:

  • Defined using module <ModuleName> (<port_list>);.

  • Instancing: Creating instances of modules within other modules.

  • Ports: Used to define inputs and outputs of a module. Types include input, output, and inout.

Data Types

  • Nets: (types include wire, tri, etc.) represent physical connections (interconnections).

  • Cannot store values; driven by other sources.

  • Registers: Used to hold values and retain state.

  • Variable types: Include integer, real, time, etc. suitable for simulation, not synthesis.

Verilog Language Rules

  • Verilog is case-sensitive and identifies names through upper/lower case letters, numbers, and underscores.
  • Lines must be terminated with semicolons (;).
  • Commenting in Verilog:
  • Single-line: // Comment
  • Multi-line: /* Comment */ (no nesting allowed).

Conclusion: Structure in Verilog

  • A typical Verilog module might look like:
  module adder(output out, input in1, input in2);
      assign out = in1 + in2;
  endmodule
  • Design encapsulation allows different parts of a system to be defined independently while still allowing for a clear and organized structure.