CSC 205 Lecture 11 - 18 Notes

Introduction to Computer Organization and Architecture

Overview of Test Structure and Purpose

• The upcoming test may not take the full class period.

• It is primarily a terminology test focused on identifying different parts of the computer based on descriptions.

• Expected duration for the test is between 30 and 40 minutes. The instructor will review the test length based on past experiences (multiplying his time by five or six).

Definition of Key Concepts

• Computer Organization: Involves the physical components and the layout of these parts within the computer.

• Computer Architecture: Concerns the behavior and communication between different parts of the computer.

• This course primarily focuses on classical architecture, especially binary architecture, and stored program concepts.

Fundamental Computer Components

Main Parts of the Computer

1. Processor (CPU): Executes programs.

2. Memory: Stores programs and associated data.

3. Input/Output (I/O) Systems: Transfers information in and out of the computer.

Stored Program Concept

• Groundbreaking idea allowing computers to process general instructions that could change based on different problems, rather than being hardwired.

CPU Architecture Components

Components of the CPU

1. Control Unit (CU): Manages data and operations within the CPU. It instructs where to send information.

2. Arithmetic Logic Unit (ALU): Performs arithmetic and logical operations including:

   • Arithmetic Operations: Addition, subtraction, multiplication, and division.

   • Logical Operations: Evaluating Boolean expressions.

3. Registers: Small storage areas in the CPU for quick access to data. They allow:

   • Data storage for operations performed by the CPU.

   • Faster access compared to main memory since operations cannot be performed directly on data in memory.

Memory and I/O Systems

• Memory holds programs and data, while I/O systems manage data transfer.

Fetch-Decode-Execute Cycle

1. Fetch: Retrieve the instruction from main memory using the Program Counter (PC).

2. Decode: The Control Unit decodes the fetched instruction.

3. Execution: The ALU performs the operation, using data from registers or fetching from memory if needed.

4. Store Result: The result is stored back into a register or memory.

Instruction Register (IR) and Program Counter (PC) Relationship

• PC indicates the address of the next instruction to be executed, while the IR holds the currently executing instruction.

Data Paths and Buses

CPU Functionality Overview

• The CPU uses internal connections called buses for communication between its components:

  • Data Bus: Carries data.

  • Address Bus: Specifies memory locations for various operations.

  • Control Bus: Handles control signals among components.

• The bus architecture allows for information transfer rather than independent execution.

Clock Speed and Processor Functionality

• A CPU has an internal clock that regulates how fast instructions are executed. Comparison of:

  • Bus Speed: Often slower than CPU speeds, with clock cycles defining the time taken to process instructions.

  • Processor Speed: Indicates how quickly the processor can perform operations but is limited by the bus speed, causing potential bottlenecks.

• Example: If a bus operates at 133 MHz, the cycle time is approximately $rac{1}{133,000,000} ext{ seconds}$ which corresponds to approximately $7.5 ext{ nanoseconds}$ per operation.

Bottlenecks in Computer Performance

• A bottleneck occurs when the fastest component (CPU) cannot execute at full speed due to slower components (e.g., bus or memory). The analogy of a band illustrates this concept where overall speed is determined by the slowest member.

Detailed Exploration of Memory

Memory Structure

• Memory Addressing: Each accessible memory location has a unique address, akin to a home address that directs to a specific house (data). Memory locations are ultimately identified by binary addresses.

• Collection of D Flip Flops represents memory, storing both bits and addresses for data retrieval.

Memory Width vs. Length

• Width: The number of bits in each memory location (e.g., width of 8 bits = byte).

• Length: The total number of available memory locations, which can be expressed via: $ext{Length} imes ext{Width}$.

• Examples: 8-bit and 16-bit widths determine how much information each memory location can store, impacting how data is segmented in memory.

Calculating Memory Capacity

• E.g., a computer with 4 megabytes of memory can be represented in binary by the formula $ext{Total Memory} = ext{Length} imes ext{Width}$ and calculated in terms of available memory bits.

• Each unique memory location needs addressing bits; thus, different configurations provide differing capacities.

Address Bits Calculation Example

• For a memory of 32 kilobytes with a width of 8 bits, if each chip contains only 2 kilobytes, calculations for the number of required chips and address bits must align to provide an effective addressable memory space.

Summary of Addressing Chips and Memory Locations

• When accessing a memory location:

  • First Four Bits indicate the chip number.

  • Last Eleven Bits indicate the specific memory location within that chip.

• For example, if given a 15-bit addressing stream:

  • Convert the first bits to denotate the chip and subsequently track the memory location within said chip to facilitate access.

Conclusion

• Understanding the interplay between CPU components, memory architecture, and bus speeds critically influences overall computer functionality. Practical illustrations, such as calculations for specific memory configurations or presentation of concepts through diagrams, will reinforce these principles. Questions and clarifications on these topics remain essential for comprehensive comprehension.