SYSTEMS LECTURE WED SEP 4th

LC-3 Subroutine Architecture: JSR and JSRR Instructions

Memory Code and Data Organization:
- In LC-3 programs, code and data are placed continuously in memory without skipping spaces between them.
- A single block of memory may contain data fields immediately followed by subroutine code.
Jump to Subroutine (JSR) Mechanics:
- JSR is an instruction used to jump from the main code to a subroutine location.
- JSR modifies execution by placing the target address of the subroutine directly into the Program Counter ( $\text{PC}$ ).
- To calculate the target subroutine address, JSR uses a $\text{PC}$ offset embedded directly within the instruction word.
- The $\text{PC}$ offset is added to the current value of the Program Counter ( $\text{PC}$ ) during instruction execution.
Bit Allocation and Range of JSR:
- Unlike load instructions (LD) which require a destination register field, JSR does not specify a register to load data into.
- Because no destination register bits are needed, JSR gains $3$ additional bits for its offset field compared to a standard $9$ -bit load instruction offset.
- JSR utilizes an $11$ -bit $\text{PC}$ offset field.
- An $11$ -bit field allows addressing across $2^{11} = 2048$ total memory locations.
- In $2$ 's complement representation, the $11$ -bit signed range spans from $1023$ (positive forward offset) down to $-1024$ (negative backward offset).
- Unlike standard load instructions which always branch forward using a positive offset, JSR supports both positive (forward) and negative (backward) offsets.
- JSR can jump down to a subroutine located lower in memory, or jump up to a subroutine located higher in memory.
Subroutine Return Mechanism and $R7$ Register:
- When JSR executes, the Program Counter ( $\text{PC}$ ) already points to the next instruction in memory immediately following JSR. This address is the designated return location.
- JSR automatically copies and saves this return address into register $R7$ ( $\text{R7}$ ) before changing $\text{PC}$ to the subroutine's address.
- The subroutine executes its sequence of instructions until it reaches the return instruction (RET).
- RET restores execution back to the caller by taking the saved address in $R7$ and copying it back into the Program Counter ( $\text{PC}$ ).
- Execution resumes seamlessly at the instruction following the initial JSR call.
- Alternative names for JSR include "Jump to Subroutine" and "Jump and Save Return".
Critical Warning Regarding Register $R7$ :
- Calling JSR automatically overwrites whatever value is currently stored in $R7$ with the return address.
- Any pre-existing data in $R7$ will be permanently lost.
- Rule: When implementing subroutines, do not use $R7$ to store general data anywhere in the program to avoid accidental data destruction.
Jump to Subroutine Register (JSRR) Mechanics:
- JSRR is a variant of JSR that uses a base register instead of an $11$ -bit $\text{PC}$ offset (analogous to how LDR relates to LD).
- The target subroutine address must be pre-loaded into a base register (e.g., JSRR R3).
- JSRR also automatically saves the return address into register $R7$ so RET can function correctly.

Control Flow Constructs and Register-Based Jumps

Range Characteristics of JSRR vs. JSR:
- JSR is restricted to target subroutines within an $11$ -bit offset range ( $1023$ locations forward or $-1024$ locations backward relative to $\text{PC}$ ).
- JSRR uses a register holding a full $16$ -bit address, enabling it to jump to a subroutine located anywhere in the LC-3 memory space.
- Course Constraint: Programs assigned in this course will not exceed $1023$ combined instructions, data items, and subroutine lines. Therefore, JSRR will not be strictly required in programming assignments, though understanding its operational mechanics is required for exams.
Jump Instruction (JMP) Mechanics:
- JMP uses a base register containing the target memory address.
- Using register-based addresses requires loading literal address values into registers.
- Hardcoding fixed address literals is functional in single-threaded processors like LC-3, but causes severe errors in multi-threaded or multi-programmed computing environments.
- JMP will not be used in course assignments; conditional/unconditional branches (BR) are used instead.
Relationship Between JMP and RET:
- RET is a specialized form of the JMP instruction.
- RET specifically executes a jump to the address contained in register $R7$ ( $\text{R7}$ ).
- In the LC-3 instruction set architecture (Appendix A), JMP and RET share the exact same binary opcode.
- Writing JMP R7 generates the exact same machine code instruction internally as writing RET.
Control Flow Constructs Using Branch (BRnzp):
- Branch instructions (BR) utilize a $9$ -bit $\text{PC}$ offset.
- If-Else Construct:
  - An unconditional branch (BRnzp) is placed at the end of the if block to jump execution over the else block.
- While Loop Construct:
  - Evaluates its condition at the top of the block prior to executing body code.
  - A conditional branch (e.g., BRn, BRz, BRp) jumps out of the loop block if the condition is false.
  - An unconditional branch (BRnzp) is placed at the bottom of the body code to jump back up to the condition evaluation at the top.
  - A standard while loop requires $2$ separate branch instructions.
- Do-While / Do-Until Construct:
  - Executes the body code first before evaluating the condition at the bottom.
  - Always executes the loop body at least once.
  - Uses a conditional branch at the bottom to jump back up to the top if the condition holds true.
  - Does not require an unconditional branch (BRnzp) at the bottom.

LC-3 Trap Routines and Memory String Representation

Standard Input/Output Traps (GETC and OUT):
- GETC: Halts execution and waits for a single character to be pressed on the keyboard. Stores the ASCII value of the character into register $R0$ .
- OUT: Takes the ASCII character stored in register $R0$ and outputs/prints it to the display terminal.
String Printing Trap (PUTS) and String Memory Layout:
- A string in LC-3 is defined as a contiguous sequence of ASCII character words in memory ended by a terminating literal zero (x0000).
- Example memory array for string "HELLO": ASCII values for 'H', 'E', 'L', 'L', 'O', followed by numeric value 0 (x0000).
- Distinction between Character Zero and Literal Zero:
  - Character '0' has an ASCII decimal value of $48$ (hexadecimal x30).
  - Literal zero is x0000 (ASCII NULL).
  - Java Analogy: Null object references in Java (p == null) point to memory address 0 (null).
- LC-3 strings are referred to as null-terminated strings.
Operating Mechanism of PUTS vs. OUT:
- Printing a single character requires loading the character's ASCII value into $R0$ and invoking OUT.
- Printing a string via PUTS requires loading the starting memory address of the string into register $R0$ using LEA (Load Effective Address).
- Internal Execution Steps of PUTS:
  1. Reads the memory value at the address provided in $R0$ .
  2. Checks if the value is equal to literal zero (x0000).
  3. If non-zero, copies the character to $R0$ , calls OUT, advances the internal memory pointer to the next consecutive address, and repeats.
  4. If zero (x0000) is encountered, execution terminates.
Code Example Comparison (Character vs. String Output):
- Character printing pattern:
  - LDR R0, R2, #2 (Loads character ASCII value 48 / x30 into $R0$ )
  - OUT
  - HALT
- String printing pattern:
  - LEA R0, STRING_LABEL (Calculates $\text{PC}$ offset to place starting address x3003 into $R0$ )
  - PUTS
  - HALT

Opcodes, Assembly Process, and Disallowed Instructions

LC-3 Opcode Usage Rules:
- Allowed Opcodes: Standard arithmetic, logical, load, store, branch, trap (GETC, OUT, PUTS, IN, HALT), JSR, and RET instructions.
- Forbidden/Disallowed Instructions for Course Programs:
  - LDI (Load Indirect)
  - STI (Store Indirect)
  - JMP (Jump — use BR or RET instead)
  - JSRR (Jump Subroutine Register — use JSR instead)
  - RTI (Return from Interrupt — used in specialized hardware interrupt handlers during the final week of class)
Software Roles: Assembler vs. Simulator:
- Assembler: A software tool that translates human-readable assembly language source code (.asm) into binary/hexadecimal machine code (.hex).
- Simulator: A software environment that loads and executes hexadecimal machine code.
- Hand-conversion to Hex:
  - Homeworks $3$ and $4$ require manually converting assembly instructions to $4$ -digit hexadecimal values.
  - Homework $5$ and subsequent assignments require writing raw assembly source files (.asm). Hand conversion to hex is not performed for Homework $5$ onward.
- Grading Pipeline: .asm files uploaded to WebCat are automatically assembled into machine code and executed against test cases.

Assembler Directives (Pseudo-ops)

Definition of Pseudo-ops:
- Pseudo-ops (assembler directives) are instructions written to give directions directly to the assembler software during compilation.
- Pseudo-ops always begin with a period / dot (.).
- They do not correspond directly to CPU hardware opcodes executed at runtime.
Origin Directive (.ORIG):
- Syntax: .ORIG x3000
- Specifies the starting memory location where the assembled machine code will be loaded.
- Must be the very first meaningful statement in the source file.
- Only blank lines and comment lines are permitted above .ORIG.
- Must appear exactly once per program file.
- If omitted, the assembler will fail, issue errors, or incorrectly misinterpret the first program instruction as the origin address.
Data Allocation Directives:
- .STRINGZ:
  - Syntax: `.STRINGZ