EENG3150 Digital Technologies - Lecture 4

Sequential Logic - Lecture 4

Applications of Flip-Flops

• Data registers

• Shift registers

• Divide-by-2 operation

• Parallel-to-Serial converter

• Serial-to-Parallel converter

• Sequence generators

• Counters

• Binary counters

• BCD (binary coded decimal) counters

Counters

• Feedback Q to D

• Q{t+1} = Qt

• Timing Diagram (Rising edge triggered flip-flops)

  • Shows the relationship between CLK (Clock), D (Data), and Q (Output) signals.

One-Bit Counter

• Modulo-2 counter

• Base 2 counter

• Counts from 0 to 1

• Output is half the input frequency

• Number of clocks vs. Q output:

  • 0: Q = 0

  • 1: Q = 1

  • 2: Q = 0

  • 3: Q = 1

  • 4: Q = 0

  • 5: Q = 1

2-Bit Counter

• Rising edge triggered flip-flops

• Includes CLK, D1, Q1, D2, and Q2 signals.

Timing Diagram - 2-Bit Counter

• Illustrates the relationship between CLK, Q1, and Q2 over time.

• Shows the count sequence based on clock cycles.

• Q1 and Q2 represent the two bits of the counter.

2-Bit Counter - Operation and Function

• 2-bit counter

• Modulo-4 down counter

• Counts 3 -> 2 -> 1 -> 0

• Q_2 is MSB (most significant bit)

• Q_1 is LSB (least significant bit)

2-bit Up Counter

• Required sequence: 0 -> 1 -> 2 -> 3 (counts up from 0)

• Q2 Q1 sequence:

  • 0 0

  • 0 1

  • 1 0

  • 1 1

• Q_2 changes under specific conditions.

2-bit Up Counter - Implementation

• Q2 changes when Q1 goes from 1 to 0.

• To achieve this:

  • Use negative edge triggered flip-flops

  • Use \overline{Q1} instead of Q1 to clock flip-flop 2

• Different configurations of D1 and D2 for achieving the up-counter functionality.

2-bit Up Counter - Negative Edge Triggered Flip-Flops

• Illustrates the count sequence 1 -> 2 -> 3 -> 0 -> 1 -> 2 with negative edge triggered flip-flops.

• Shows the timing diagram with CLK, Q1, and Q2 signals.

2-bit Up Counter - Clocking with \overline{Q_1}

• Uses \overline{Q1} instead of Q1 to clock the second flip-flop.

• Asks to show Q2 and Q1 in the timing diagram.

2-bit Up Counter - Timing Diagram with \overline{Q_1}

• Illustrates the count sequence 1 -> 2 -> 3 -> 0 -> 1 -> 2 with \overline{Q_1} clocking the second flip-flop.

• Shows the timing diagram with CLK, Q1, and Q2 signals.

Binary Counter - Counting Range

• Relationship between the number of flip-flops, count range, and modulus of the counter.

• N flip-flops:

  • Count range: 0, 1, 2, 3, … , 2^N - 1

  • Modulus of counter: 2^N

• Examples:

  • 1 flip-flop: Count range 0, 1; Modulus 2 (2^1)

  • 2 flip-flops: Count range 0, 1, 2, 3; Modulus 4 (2^2)

  • 3 flip-flops: Count range 0, 1, 2, 3, 4, 5, 6, 7; Modulus 8 (2^3)

BCD (Binary Coded Decimal) Counter

• BCD representation of decimal numbers 0-9.

• Decimal to BCD conversion:

  • 0 -> 0000

  • 1 -> 0001

  • 2 -> 0010

  • 3 -> 0011

  • 4 -> 0100

  • 5 -> 0101

  • 6 -> 0110

  • 7 -> 0111

  • 8 -> 1000

  • 9 -> 1001

BCD Counter - Implementation

• 4-bit up counter with additional logic to reset the counter when it reaches 10 (1010 in binary).

• Utilizes a