control unit coa

Control Unit Overview

The Control Unit (CU) directs operations within the CPU and generates the control signals necessary for executing instructions.
There are two main types of control units:
- Hardwired Control Unit
- Microprogrammed Control Unit

Fetch
- Retrieves the instruction from memory.
- The instruction is stored in the Instruction Register (IR).
- The Program Counter (PC) is updated to point to the next instruction.
Decode
- Decodes the fetched instruction to identify the operation and operands.
Execute
- The ALU performs computations, manipulates registers, or issues memory accesses based on the decoded instruction.
Store Result (if applicable)
- Writes back results to memory or registers.

Memory Address Register (MAR): Holds the address in memory for read/write operations.
Memory Buffer Register (MBR): Contains the data to be written or the data that was read.
Program Counter (PC): Points to the next instruction in memory.
Instruction Register (IR): Holds the current instruction being executed.

Fetch Phase
- Move PC to MAR, issue a Read command to memory.
- Copy read data to MBR.
- Move data from MBR to IR.
- Increment PC.
Decode Phase
- IR holds the opcode and operands; CU interprets it.
- Determines the type of instruction (e.g., memory reference, register reference).
Execute Phase
- Executes the operation indicated by the opcode, using appropriate addressing modes.
- Access memory or registers as required; uses ALU for operations.
Results Handling
- If the result needs to be stored, move data from registers to memory or relevant registers.

A microprogrammed control unit utilizes a sequence of microinstructions stored in control memory to generate control signals.
Control Memory is where these microinstructions and data are stored, facilitating flexibility and ease of updates.

Less Complex: Compared to hardwired units, these can handle complex instructions more flexibly.
Speed: Generally slower than hardwired units due to the additional layer of interpretation needed for microinstructions.

Uses fixed hardware to generate control signals, such as decoders and combinational logic circuits.
Faster execution than microprogrammed units, but typically more complex and tougher to modify.

Advantages:
- Faster signal generation, optimized for speed.
- Suitable for simpler CPU designs and RISC architectures.
Disadvantages:
- Complexity increases with the number of instructions.
- Difficult to modify control signals which burdens upgrades or adding new features.

Zero Address Instruction: No explicit operands, typically used in stack-based architecture.
One Address Instruction: Implies an accumulator where one address is specified.
Two Address Instruction: Specifies two addresses for operations, allows storing result in a different location than the source.
Three Address Instruction: Allows for operations with three operands, enhancing flexibility and parallel processing capabilities.

Pipelining allows overlapping instruction execution (fetch, decode, execute stages) to improve CPU throughput.
Stages: Typically includes instruction fetch, decode, execute, memory access, and write-back.

Speedup: The ratio of non-pipelined execution time to pipelined execution time, ideally less than or equal to the number of stages.
Throughput: Number of instructions completed per unit time, gauging performance improvements due to pipelining.
Pipelining exposes many dependencies that can introduce stalls or hazards, necessitating efficient design practices.

Speedup and throughput metrics help in evaluating the benefits of pipelined architecture over non-pipelined architecture.