Operating Systems (REAL)

The evolution of operating systems is famed as A Story In Three Acts, where the OS uses clever hardware and software illusions to manage hardware constraints.


The kinds of operating systems

  • Desktop → runs on normal desktops/laptops; often tuned for consumer use-case. (Linux, OSX and Windows are examples)

  • Server → runs on servers, often headless and tuned fir server workloads. Prioritises throughput, extreme stability, and hardware scalability. (Hundreds of CPU cores, hundreds of gigabytes of RAM, terabytes of storage and accelerators)

  • Embedded → in cars, smart tvs, printers, routers, washing machines etc. Typically run for long periods of time with few updates, sometimes in difficult environments, with zero erros and few or no updates.

  • Mobile → Android, IOS etc. These are more advanced versions of embedded OS; approximating a desktop OS but with stricter power management.

  • Realtime → in missiles, assembly-line microcontrollers, pacemakers etc. If a task isnt completed on time, deterministically, then the consequences can be VERY bad


The CPU

Overview of CPU Architecture and Hardware Execution Units


The CPU core with reference to relevant OS state


The memory hierarchy

Act 1: Lying About Memory

The Core Problem and The Illusion

In early computing, programs grew larger than physical RAM (like trying to run 100KB programs on 32KB RAM systems). Manual programmer tricks were prone to errors and fragile. Like overwriting memory segments on the fly.

To combat this, The OS and hardware collaborate to present each process with it’s own large, private virtual address space rather than direct physical memory with addresses.

This is done by dividing the virtual memory into fixed-size blocks called pages, while the physical RAM is divided into matching page frames that are mapped to a page table.

Demand Paging and Page Faults

When launching an application, the OS loads only the initially required pages into RAM and then it ‘lies‘ to the process, pretending the entire program is loaded. This is Demand Paging.

The Memory Management Unit (MMU) then checks the process’s page table to map Virtual Page Number(VPN) to Physical Frame Numbers (PFN). This is the Address Translation Process.

Now, If a process is loaded ito RAM, it translates the virtual address to the actual page address and the it reads/writes/executes there. However, If a process accesses a page that is not yet loaded into the RAM:

  1. The MMU triggers a page fault (which is essentially a hardware exception).

  2. Control transfers to an OS Trap Handler / Interrupt Service Routine (ISR)

  3. The OS finds a free page frame (or it evicts a victim page), reads in the missing data from disk storage into RAM and then updates the page table.

  4. The MMU restarts the original instruction seamlessly

This is the method of Page Fault Handling.

Since each process has its own page table mapping to distinct physical frames, processes cannot access or corrupt each other’s memory space, providing security and isolation as a byproduct of address translation. This is known as Process Isolation.

Key Hardware and Software Optimisations

  • Looking up oage tables before every memory access doubles the RAM latency, that is why we have the TLB. The Translation Lookaside Buffer is an on-chip hardware cache that stores recent virtual-to-physical address mappings to restore full memory speed.


  • Flat page tables for large address spaces waste huge amounts of RAM storing unmapped entries (such as the empty space between the heap and the stack). Multi-level hierarchical page tables allocate sub-tables dynamically only as needed


  • Flags stored in page table entries enforce control and security by:

  1. Indicating whether the page is currently in physical RAM with the Present Bit

  2. Showing if the page was modified (requiring a write-back to disk if evicted) with the Dirty Bit .

  3. An Execute-Disable / No-Execute bit to prevent code execution from data memory.

  4. Checking whether or not a page has been referenced with the Accessed Bit.

  5. Checking if the userspace can access this specific part of memory with the Users/Supervisors bit.

  6. and checking if the page is writeable with the Write Bit.


  • Using fixed page sizes eliminates external memory fragmentation(essentially searching for variable-sized chunks), but introduces internal fragmentation (unused space inside a page). The OS uses slab allocaters to reduce internal fragmentation when allocating frequent kernel objects.






Act 2: Lying About Processing

The Core Problem and Multiprogramming

The Constraint for Processors was that I/O(Input Output) operations are orders of magnitude slower than CPU execution. In early batch systems(loaders, resident monitors), the CPU sat idle waiting for slow I/O transfers to finish.

To combat this, the OS creates the illusion/lie that multiple programs run simultaneaously on a single CPU core by switching execution between tasks during idle periods.

To prevent a single program from hogging the CPU (like getting stuck in an infinite loop), the OS uses a hardware timer to forcibly preempt tasks when their allocated time quantum expires.


Process States and The Process Control Block (PCB)

The process scheduler tracks processes across 5 core states. This is the Process lifecycle and it goes as follows:

  • New → Process is created and pages begin loading.

  • Ready → Waiting in the queue for CPU time.

  • Running → Currently executing on the CPU core.

  • Blocked → Waiting for I/O completion, a lock, or a page fault.

  • Terminated → Finished execution (exit())


When an OS creates a process, it maintains a PCB containing:

  • Identifiers → Process ID (PID), Parent PID (PPID), User ID (UID).

  • Execution Context → Saved general-purpose register, Program Counter (PC), Stack Pointer (SP), and page table pointer.

  • Scheduling & Resource State → Current process state, priority metrics, and open device handles.


Scheduling Algorithms and Metrics

The scheduler determines who runs next and for how long, evaluating the perfomance using :

  • Waiting Time → Total time a process spends sitting in the ready queue.

  • Turnaround Time → Total time elapsed from process arrival to final completion.

  • Response Time → Time from arrival until the process first gets to execute (critical for interative response latency)

Aswell as two distinct Algorithms

  • First-Come, First-Served (FCFS) → Non-preemptive FIFO queue, runs each process until it completes or blocks on I/O.

  • Round Robin (RR) → Preemptive FIFO queue, runs each process for a fixed time quantum before placing it at the back of the queue.



Hardware Interrupts and Events

Early software repeatedly polled devices (“Are you done yet?“), wasting CPU cycles, whereas with modern hardware, we use Interrupts, where I/O devices signal the CPU over hardware lines when data is ready.

To balance speed and responsiveness, interrupt handlers are split into two halves:

  • Top-Half → Executes immediately, handles urgent, fast, non-blocking tasks with interrupts disabled.

  • Bottom-Half → Deferred, handles slower background processing with interrupts re-enables


Software/Hardware events are classified into:

  • Synchronous Faults → The PC points to the faulting instruction, control returns to re-execute the same instruction after resolving the issue.

  • Synchronous Traps → The PC points to the next instruction, used for intentional system calls (syscall)

  • Asynchronous Interrupts → Triggered externally by hardware, the PC points to the next instruction, allowing execution to resume once the event finishes.