Logic Gates & Integrated Circuits – Comprehensive Study Notes

Logic Gates

• Electronic circuits within digital systems that execute logical operations on binary information (digital signals) and regulate data flow.
• Accept 1-or-more inputs ➜ yield a single output (HIGH = 1, LOW = 0).
• Fundamental building blocks of digital ICs (computers, smartphones, memory, etc.).
• Representations of gate behaviour
  • Truth table (a.k.a. function table)
  • Boolean (algebraic) expression
  • Timing (wave-form) diagram

Seven Fundamental Gates & Three Taxonomies

• Basic Gates → AND, OR, NOT
• Universal Gates → NAND, NOR (capable of synthesising any Boolean function)
• Special Gates → XOR, XNOR (exclusive versions of OR / NOR)

Basic Gates

AND Gate

• Logical multiplication; symbol $X = A \cdot B$ (for 2-input).
• Outputs HIGH only when all inputs HIGH.
• Series–switch analogue: two closed switches in series allow current to bulb.
• Truth table (2-input) 0 0→0, 0 1→0, 1 0→0, 1 1→1.
• Applications: gating/​enabling data paths, digital transmission control, measuring instruments, alarms.

OR Gate

• Logical addition; symbol $X = A + B$.
• Output HIGH if any input HIGH; all LOW yields LOW.
• Parallel-switch example (bulb lights if any switch closed).
• Applied in alarm systems: any sensor HIGH activates alarm.

NOT Gate (Inverter)

• Complements a single input; symbol $X = \overline{A}$.
• Switch example: open switch diverts current to bulb (bulb ON when switch LOW).
• Used for 1’s complement generation inside binary arithmetic units, esp. subtraction via complementing.

Universal Gates

NAND Gate

• “NOT AND”: AND followed by inversion; symbol resembles AND with “bubble”.
• Truth table (2-input): only HIGH→LOW; any LOW→HIGH.
• Timing diagram demonstrates inversion of AND waveform.
• Functional syntheses using only NANDs:
  • NOT: tie inputs ➜ $\overline{A}$.
  • AND: cascade two NANDs.
  • OR: three-NAND network leveraging De-Morgan.

NOR Gate

• “NOT OR”: OR followed by inversion; symbol = OR + bubble.
• Truth: all LOW→HIGH; any HIGH→LOW.
• Functional syntheses using only NORs:
  • NOT: tie inputs ➜ $\overline{A}$.
  • OR: cascade two NORs.
  • AND: triple-NOR network (inputs first inverted).
• Cross-synthesis:
  • NOR from NAND network (NAND OR-function plus inverter).
  • NAND from NOR network (NOR AND-function plus inverter).

Special Gates

XOR (Exclusive OR)

• Outputs HIGH when number of HIGH inputs is odd.
• 2-input expression $X = A\, \overline{B} + \overline{A}\,B$ or $A \oplus B$.
• Constructed from inverters, ANDs, OR.
• Key in half/full adders and parity functions.

XNOR (Exclusive NOR)

• XOR + inversion; outputs HIGH when HIGH input count is even.
• 2-input expression $X = A\,B + \overline{A}\,\overline{B}$.
• Symbol = XOR with bubble.

Integrated Circuits (ICs)

• 1958 invention (Jack Kilby); first commercial 1961.
• Multiple components fabricated on single semiconductor chip; dedicated function, high speed, reliability, low power/​cost.
• Examples: microcontroller in TV for remote decoding & display control; ubiquitous in computers, phones, medical, industrial, security, household, toys.

Application-Based Categories

• Analog IC: processes continuous signals (op-amps, regulators, filters, sensors, oscillators).
• Digital IC: discrete (binary) signals (logic, multiplexers, flip-flops, microprocessors).
• Mixed-Signal IC: combine analog & digital (ADC, DAC, timers).

Integration-Level (Gate Count) Generations

• SSI (Small-Scale) < 10 gates.
• MSI (Medium-Scale) < 100 gates (decoders, adders, registers).
• LSI (Large-Scale) < 10 000 gates (processors, memory, PLDs).
• VLSI (Very-Large-Scale) < 100 000 gates (complex micro-computer chips).
• ULSI (Ultra-Large-Scale) > 100 000 gates (very-large memories, high-end microprocessors).

Packaging & Pin-Identification

• Chip encased in plastic/ceramic for protection; pins 14 → 64 +.
• Standard numbering: locate Notch or Dot → pin 1 at lower-left, count anticlockwise.

Fixed-Function vs Programmable ICs

• Fixed-Function: logic hard-wired by manufacturer (e.g. $74HC08$ = four 2-input ANDs; “74” series prefix, family code HC = High-speed CMOS, “08” function code).
• PLDs/​FPGAs covered in later chapter.

IC Implementation Technologies

• All gates realised via transistors acting as switches.

Transistor Classes

1. BJTs (Bipolar Junction Transistors)
   • 3-terminal NPN/PNP; Emitter (E), Base (B), Collector (C).
   • Junction biases:
   – Forward (allow current; ≈$0.7\,\text V$ silicon drop).
   – Reverse (block current, small leakage).
   • Switch behaviour: Base > 0.7 V → ON (closed); Base < 0.7 V → OFF (open).
2. MOSFETs (Metal-Oxide-Semiconductor FETs)
   • 4 terminals: Source (S), Gate (G), Drain (D), Body (B) (Body often tied to Source).
   • Unipolar (single carrier type). Two polarities: N-channel, P-channel.
   • Gate controls conduction channel.
   • Switching examples:
   – N-channel: $V<em>G$ high → ON (closed); $V</em>G = 0$ → OFF.
   – P-channel opposite polarity.

Logic Families

Each family = set of ICs with common electrical characteristics & fabrication.

TTL (Transistor-Transistor Logic)

• BJT based; $V_{CC} = 5\text{ V}$.
• Logic ranges: 0\text{ V} \le V < 0.7\text{ V} = LOW, $2.7\text{ V} \le V \le 5\text{ V}$ = HIGH.
• Propagation delay ≈$9\text{ ns}$; power ≈$10\text{ mW/gate}$.
• NAND gate realisation analysed (transistors Q1-Q4, resistors R1-R4, diodes D1-D3).
• Sub-families: Standard, Low-Power, High-Speed, Schottky, Advanced Schottky.

ECL (Emitter-Coupled Logic)

• BJT, emitters tied together; devices never saturate → ultrafast (0.5-2 ns).
• Negative supply: $V_{EE} = -5.2\text{ V}$, ground = 0 V.
• Logic 1 ≈$-0.8\text{ V}$, Logic 0 ≈$-1.7\text{ V}$ (≈$0.85\text{ V}$ swing).
• High power ≈$30\text{ mW/gate}$; used in super-computers, high-speed links.
• Core cell implements OR & NOR simultaneously (dual outputs).

MOS Families

• PMOS (P-channel, operates on negative supply): NAND = parallel P-MOSFETs.
• NMOS (N-channel, positive supply): NAND = series N-MOSFETs to ground.
• High density, low power; used in memories, µ-processors.

CMOS (Complementary MOS)

• Paired N-channel & P-channel transistors (pull-up/pull-down networks).
• Lowest static power, high density; mainstay for VLSI/ULSI.
• Example 2-input NAND: P-network in parallel, N-network in series; truth per earlier section.
• Logic range $0\text{–}1.5\text{ V}$ = LOW, $3.5\text{–}5\text{ V}$ = HIGH (for 5-V CMOS).

Boolean Algebra Notes (Preview to Next Chapter)

• $\overline{A \cdot B} = \overline{A} + \overline{B}$ (De Morgan).
• $\overline{A + B} = \overline{A} \cdot \overline{B}$.
• Relations utilised in NAND/NOR functional conversions (e.g., NAND pair ⇒ AND; triple NAND ⇒ OR, etc.).

Example IC Pin-outs (74-Series)

• $74xx08$ – 4× 2-input AND (14-pin).
• $74xx32$ – 4× 2-input OR.
• $74xx04$ – 6× NOT.
• $74xx00$ – 4× 2-input NAND.
• $74xx02$ – 4× 2-input NOR.
• $74xx86$ – 4× 2-input XOR.
• $74xx66$ – 4× 2-input XNOR.

Power/Ground pins are typically 14 & 7 (or top-right/bottom-left) for dual-in-line package (DIP).

Summary of Key Numerical Parameters

• TTL: $V<em>{CC}=5\text{ V}$, $t</em>p\approx9\text{ ns}$, $P_{diss}\approx10\text{ mW}$.
• ECL: $V<em>{EE}=-5.2\text{ V}$, $t</em>p=0.5\text{–}2\text{ ns}$, $P_{diss}\approx30\text{ mW}$.
• CMOS: $P_{static} \ll 1\text{ µW/gate}$ (leakage only), delay similar to TTL.

Practical / Ethical / Real-World Context

• High integration enables compact consumer electronics; also raises e-waste & power-consumption ethics.
• Security: logic gate synthesis used in cryptographic hardware (XOR for mixing, NAND/NOR for obfuscation).
• Safety-critical: redundancy via universal gates allows fail-safe designs.