Fetch, Decode, Execute Cycle of Von Neumann Machine COMPSCI110 LEC13

  • Overview of the Von Neumann Machine

    • Has four major components:

    • Memory Unit

    • Arithmetic and Logic Unit (ALU)

    • Input/Output Unit

    • Control Unit

  • Fetch, Decode, Execute Cycle

    • Continuous process in which the CPU executes instructions.

Fetch Phase

  • Step 1: Transfer Program Counter to Memory Address Register (MAR)

    • The Program Counter (PC) holds the address of the next instruction to fetch.

    • Example: If PC points to address 2, its value is transferred to the MAR.

    • MAR is the register that interfaces directly with memory to fetch values.

  • Step 2: Memory Decoder Circuit

    • The MAR value is decoded by the memory decoder circuit to select the correct memory location.

    • A specific line in the memory is chosen based on the binary value contained in the MAR.

  • Step 3: Control Unit Initiates Fetch

    • A fetch signal is sent from the control unit indicating a read operation from memory.

    • Memory Data Register (MDR) temporarily holds fetched data from memory. The flow is from memory to the MDR.

  • Step 4: Copy from MDR to Instruction Register (IR)

    • The value in MDR is copied to the Instruction Register (IR), which holds the instruction to execute.

    • The IR is a special register as it acts as a buffer between the fetched instruction and the CPU's execution process.

  • Step 5: Increment Program Counter

    • The PC is incremented to point to the next instruction in memory.

    • If the original PC value was 2, it changes to 3, preparing for the next fetch cycle.

Decode Phase

  • The control unit decodes the instruction in the IR to understand what action is required.

  • Instruction Format

    • 16 bits wide:

    • First 4 bits: Opcode

    • Last 12 bits: Memory Address

  • Example Instruction: "LOAD 100"

    • Opcode for LOAD is 0000 and the memory address for 100 in binary is appended (let's say 01100100 for 100).

    • Thus the entire instruction in the IR would look like 000001100100.

    • The control unit uses the opcode to activate the appropriate line in a decoder circuit, determining the instruction type.

Execute Phase

  • Executing the instruction determined in the decode phase. Steps vary depending on the instruction type.

  • Example: LOAD Instruction Execution

    • LOAD X: Transfer content of memory address X to register R.

    • Step-by-Step Execution:

    1. Transfer the address from IR to MAR:

      • The memory address from the IR (which would be 100) is placed into the MAR.

    2. Initiate fetch to get value into MDR:

      • A fetch signal is sent to retrieve the value stored at address 100 from memory to the MDR.

      • If address 100 holds the value 20, then 20 is now in the MDR.

    3. Copy value from MDR to register R:

      • The value from the MDR (20) is then copied into register R.

      • Now R holds the value 20, which the CPU can use for further operations.

  • Example Execution of Other Instructions:

    • STORE X:

    • Store the contents of register R into the memory address X.

    • Execution Steps:

      1. Transfer the value from R to MDR.

      2. Set MAR to address X.

      3. Write the value in MDR back to memory location X.

    • ADD X:

    • Update register R to be equal to the sum of the current value in R and the contents of memory address X.

    • Execution Steps:

      1. Load the value from address X into another temporary register (let's call it T).

      2. Add the value in T to R.

      3. Store the new value back in R.

    • JUMP X:

    • Direct the program counter (PC) to the specified memory address X.

    • Execution Steps:

      1. Transfer the address from IR to PC, redirecting the flow of the program to the new address.

    • COMPARE X:

    • Compare the contents of memory address X with the value in register R, setting flags accordingly.

    • Execution Steps:

      1. Transfer address X to MAR.

      2. Fetch the value at address X into MDR.

      3. Compare the fetched value in MDR with the value in R, setting specific flags for greater than, less than, and equals.

Additional Notes

  • Memory Data Register: Can hold instructions or data since Von Neumann architecture utilizes the same memory for both.

  • Each type of instruction may require different steps during the execute phase, although fetching and decoding are similar.

  • The systematic approach of the fetch-decode-execute cycle is pivotal for the smooth operation of the Von Neumann architecture, highlighting the critical roles of its various components in instruction processing.