Digital Systems 2: Signal Conversion and Processing Notes

Logistics and Test 2 Arrangements

• Test 2 Scheduling Discordance: There was a discussion regarding the date for the Digital Systems 2 Test 2.

  • Some students believed the test was moved to the 28th based on a group vote.

  • The lecturer clarified that the test must remain on May 25th at $14:00$ ($02:00\,\text{PM}$).

  • The 28th choice is impossible because marks must be captured into the system by that date. Delaying the test to the 28th would not allow time for marking and collation of prep marks.

  • Per departmental instruction, the test window for Test 2 starts on the 18th and ends on the 26th.

• Pre-Test Timeline: Tasks or specific preparatory materials will be released around Sunday, May 24th. The test will proceed on Monday, May 25th.

• Scope of Test 2: The test covers three primary chapters/topics:

  • Shift Registers.

  • Memories and Storage.

  • Data Processing and Control.

  • Signal Conversion and Processing (the current chapter).

Introduction to Signal Conversion and Processing

• Overview: This is the final chapter in the Digital Systems 2 syllabus. It focuses on signal handling, specifically the transition between analog and digital domains.

• Process Flow:

  • Transmit Side: An analog signal is generated at the initiating terminal and must be converted into digital form (binary stream of $0$s and $1$s) for line transmission.

  • Receive Side: The incoming bit stream is accepted by the receiver and converted back into its original analog form.

• Core Components:

  • ADC: Analog-to-Digital Converter.

  • DAC: Digital-to-Analog Converter (sometimes referred to as DA converter).

Sampling Theory and the Nyquist Criterion

• Sampling Definition: Sampling is the process of taking a number of discrete values from an analog signal at specific points in time to help reshape the waveform.

• Sampling Intervals: Samples are taken at regular intervals, and the value of each sample depends on the amplitude of the analog signal at that specific moment.

• Harmonics: Harmonics are supplementary frequencies that appear in multiples of the center frequency (sine waves of different frequencies and amplitudes). Generally, distant amplitudes have less effect as they fade from the center frequency.

• The Sampling Theorem (Nyquist Criterion): To accurately reproduce an analog signal, the sampling frequency ($f_s$) must be at least twice the highest frequency component ($f_{max}$) present in the original modulating signal.

  • Formula: $f_s \ge 2 \times f_{max}$

  • The frequency $f_{max}$ is often referred to as the Nyquist frequency in the context of the highest component needing to be captured.

• Common Industry Applications:

  • Digital Audio/CDs: Most music have a high frequency component of approximately $20\,\text{kHz}$. Using a cushion, CDs utilize a sampling rate of $44.1\,\text{kHz}$ (sometimes generalized as $44\,\text{kHz}$) to capture frequencies up to $22\,\text{kHz}$. High-end audio equipment may use sampling frequencies above $48\,\text{kHz}$.

  • Telecommunications/Speech: Normal human speech falls within a $4\,\text{kHz}$ band. Therefore, communication systems use a standardized sampling frequency of $8\,\text{kHz}$.

Aliasing and Filtering

• Anti-Aliasing Filter: An "anti-alias" filter is used to nullify portions of a signal that would cause errors. "Alias" essentially means "part of" or "belongs to."

• Aliasing Error: If the sampling frequency is less than twice the maximum analog frequency (f_s < 2 \times f_{max}), the frequency spectrums overlap. In the overlap area, the system cannot distinguish which signal the data belongs to. This creates an alias—a false signal.

• Low Pass Filtering: Low-pass filters are implemented to remove harmonics greater than the sampling frequency. This ensures the frequency spectrums for the analog signals do not overlap, thereby eliminating aliasing errors.

The Process of Analog-to-Digital Conversion (ADC)

• Step-by-Step Conversion:

  1. Sampling: Discretizing the continuous analog signal based on a sampling frequency.

  2. Sample and Hold: A circuit captures the amplitude of a sample and "holds" that specific voltage level constant across the duration until the next sample is taken. This creates a "staircase" appearance where discrete amplitudes are held across the intervals.

  3. Quantization: The process of assigning a specific binary code value to the corresponding sampled analog amplitude. The signal is read against a binary scale or code level.

• Bit Depth and Levels:

  • A $2$-bit code provides $2^2 = 4$ levels ($00$, $01$, $10$, $11$).

  • A $4$-bit code provides $2^4 = 16$ levels.

  • Accuracy: When a value like $10.5$ is converted by a calculator or system, it typically captures the integral part ($10$) as the binary code (e.g., $1010$). Manual conversion is required for fractional parts, but standard quantization often rounds to the nearest level.

Operational Amplifiers in Signal Conversion

• Op-Amp as a Comparator: The central component of an ADC is the Operational Amplifier (Op-Amp) used in a comparator configuration.

  • Non-inverting input ($V_+$): Connected to the input signal.

  • Inverting input ($V_-$): Connected to a reference voltage.

• Comparator Logic:

  • If V_+ > V_-, the output is a Logic $1$ (Positive logic prevails).

  • If V_+ < V_-, the output is a Logic $0$.

  • If $V_+ = V^-$, theoretically the positive logic prevails (Logic $1$), though circuits try to avoid this ambiguity through priority encoding.

The FLASH (Simultaneous) ADC Method

• Mechanism: This is a high-speed method using a network of resistors and multiple comparators.

• Resistor Divider Network: A series of equal resistors ($R$) are connected to a reference supply voltage ($V_{ref}$). This creates multiple reference voltage levels (voltage dividers).

  • Example: For an $8\,\text{V}$ supply with $8$ resistors, each resistor drops $1\,\text{V}$. Points in the network will have reference voltages of $1\,\text{V}$, $2\,\text{V}$, $3\,\text{V}$, etc.

• Operation Example:

  • Given an input sampled voltage of $3.4\,\text{V}$.

  • This $3.4\,\text{V}$ is compared simultaneously against the reference voltages ($1\,\text{V}, 2\,\text{V}, 3\,\text{V}, 4\,\text{V}, \dots$).

  • Comparators at levels $1\,\text{V}, 2\,\text{V},$ and $3\,\text{V}$ will output Logic $1$ because 3.4 > 1, 3.4 > 2, and 3.4 > 3.

  • Comparators at levels $4\,\text{V}$ and above will output Logic $0$ because 3.4 < 4.

  • A priority encoder then takes the highest active line (Line $3$) and converts it to a binary code (e.g., $011$ for a $3$-bit system).

The Successive Approximation Register (SAR) ADC Method

• Mechanism: SAR is a common ADC method that uses a DAC (Digital-to-Analog Converter) within its internal feedback loop. It performs a "binary search" to find the digital equivalent of an analog input.

• The "Keep or Reset" Logic:

  • Rule 1: Logic $0$ output from the comparator means Reset (Clear the bit).

  • Rule 2: Logic $1$ output from the comparator means Keep (Maintain the bit).

• Operation Example ($4$-bit system, weighting $8-4-2-1$):

  • Input Voltage: $5\,\text{V}$.

  • Step 1: Set the Most Significant Bit (MSB, $2^3$) to $1$; others to $0$ ($1000$, value = $8$). Compare $5\,\text{V}$ to $8\,\text{V}$. Since 5 < 8, output is $0$. Reset MSB to $0$.

  • Step 2: Set the next bit ($2^2$) to $1$ ($0100$, value = $4$). Compare $5\,\text{V}$ to $4\,\text{V}$. Since 5 > 4, output is $1$. Keep this bit.

  • Step 3: Keep previous bit and set the next bit ($2^1$) to $1$ ($0110$, value = $6$). Compare $5\,\text{V}$ to $6\,\text{V}$. Since 5 < 6, output is $0$. Reset bit to $0$.

  • Step 4: Keep previous "Keep" bits and set LSB ($2^0$) to $1$ ($0101$, value = $5$). Compare $5\,\text{V}$ to $5\,\text{V}$. Result is Logic $1$. Keep this bit.

  • Final Result: The digital output is $0101$.

Errors in Analog-to-Digital Conversion

• Typical ADC Errors:

  1. Missing Code: A specific binary code is skipped or never output, even when the input voltage is in the correct range. The ramp is interrupted.

  2. Incorrect Code (Bit Stuck): Caused by a specific bit being permanently "stuck high" (Logic $1$) or "stuck low" (Logic $0$). This ruins the linear progression of the binary values.

  3. Offset Error: The conversion does not start at zero. For example, the ramp might start at a value of $2$ instead of $0$.

Digital-to-Analog Conversion (DAC) Fundamentals

• Process: Taking digital binary values and converting them to a proportional analog voltage or current.

• Bilateral Weighted Input DAC: This method resembles a summing amplifier (adder) from electronics. It uses an Op-Amp in an inverting configuration, meaning the output voltage ($V_{out}$) will be the negative of the sum of the inputs.

Binary Weighted Input DAC

• Resistor Weighting: The resistors are assigned values in a binary-weighted fashion (e.g., $R, 2R, 4R, 8R$).

• Crisscross Weighting Relationship:

  • The Smallest Resistor ($R$) is assigned to the Most Significant Bit (MSB) because it allows the most current to flow.

  • The Largest Resistor ($8R$) is assigned to the Least Significant Bit (LSB) because it allows the least current to flow.   

• Formulas and Calculations:

  • Current through a branch ($I$): $I = \frac{V_{supply}}{R_{branch}}$

  • Output Voltage Contribution: $V = -(I \times R_F)$, where $R_F$ is the feedback resistor.

  • Example: For a $4$-bit DAC with $V_{supply} = 5\,\text{V}$ and R_F = 10\,\text{k\Omega}, each bit has an individual scaled voltage value (e.g., MSB $D_3 = -2\,\text{V}$, LSB $D_0 = -0.025\,\text{V}$). If the input is $1111$, all current contributions are added together to reach a maximum negative output (e.g., $-3.75\,\text{V}$).

Questions & Discussion

Question regarding viewing marks: Some students mentioned they cannot see their marks for Test 1 while others can. Response: The lecturer confirmed he made the marks available for all groups. If it is only a few individuals, it might be a profile issue; if it is a whole group, it requires deeper investigation. He will check the group settings and individual profiles.

Question regarding ending the session: A student requested to end the class early to prepare for a practical session at $13:45$ ($01:45\,\text{PM}$). Response: The lecturer agreed and concluded the session after finishing the explanation of the Binary Weighted Input DAC. The next topic will be the R-2R ladder network.