Digital Logic Structures and Sequential Logic Structures

The microprocessor, a central component of computer systems, is constructed from millions of transistors. Examples of transistor counts in historical processors include:
- Intel Pentium 4 (released in $2000$ ): $48 \times 10^6$ transistors.
- IBM PowerPC 750FX (released in $2002$ ): $38 \times 10^6$ transistors.
- IBM/Apple PowerPC G5 (released in $2003$ ): $58 \times 10^6$ transistors.
At a logical level, a transistor functions as a switch. These switches are combined to create fundamental logic functions, including AND, OR, and NOT gates.
These basic gates are further integrated into higher-level digital structures such as adders, multiplexers (MUX), decoders, and registers.
The culmination of these structures allows for the building of complex processors, such as the LC-3.

Computers utilize Metal Oxide Semiconductor (MOS) transistors, which come in two complementary types: n-type and p-type.
Switch-based circuits represent binary states where values are associated with physical conditions: on/off, open/closed, or voltage/no voltage.
For an n-type MOS transistor:
- When the Gate has a positive voltage (logic $1$ ), it acts as a closed switch (short circuit between terminals).
- When the Gate has zero voltage (logic $0$ ), it acts as an open switch (open circuit between terminals).
- Terminal #2 of an n-type transistor must be connected to Ground ( $GND$ or $0\text{V}$ ).
For a p-type MOS transistor:
- When the Gate has a positive voltage (logic $1$ ), it acts as an open switch.
- When the Gate has zero voltage (logic $0$ ), it acts as a closed switch.
- Terminal #1 of a p-type transistor must be connected to the positive supply voltage ( $+2.9\text{V}$ ).
While various systems use different ranges for logical symbols (such as $+5\text{V}$ or $+3.3\text{V}$ ), the standard for these digital logic structures is defined as $+2.9\text{V}$ for logic $1$ .

Complementary MOS (CMOS) circuits utilize both n-type and p-type transistors together to ensure stable output levels.
Logic of CMOS components:
- p-type transistors are attached to the positive voltage and pull the output voltage UP when the input is zero.
- n-type transistors are attached to Ground and pull the output voltage DOWN when the input is one.
- Proper design ensures that for any input, the output is connected either to Ground or to the positive voltage, never both simultaneously.
Basic Logic Gate Definitions:
- NOT Gate (Inverter): Reverses the input. If input is $0$ , output is $1$ ( $+2.9\text{V}$ ). If input is $1$ , output is $0$ ( $0\text{V}$ ).
- NOR Gate: Output is $1$ only if both inputs are $0$ . It features a serial structure of p-type transistors on top and a parallel structure of n-type transistors on the bottom.
- OR Gate: Constructed by adding an inverter to the output of a NOR gate. Output is $1$ if any input is $1$ .
- NAND Gate (AND-NOT): Output is $0$ only if both inputs are $1$ . It features a parallel structure of p-type transistors on top and a serial structure of n-type transistors on the bottom.
- AND Gate: Constructed by adding an inverter to the output of a NAND gate. Output is $1$ only if all inputs are $1$ .
DeMorgan's Law allows for the conversion between AND and OR operations by inverting both the inputs and the final output.

A Combinational Logic Circuit is "stateless," meaning its output depends exclusively on the current inputs.
Decoder:
- A circuit with $n$ inputs and $2^n$ outputs.
- Exactly one output is set to $1$ for each unique input pattern.
Multiplexer (MUX):
- Consists of an $n$ -bit selector and $2^n$ inputs with a single output.
- The output signal is equal to the specific input selected by the selector bits (e.g., a $4$ -to- $1$ MUX).
Full Adder:
- Processes two bits ( $A$ and $B$ ) and a carry-in ( $C_{in}$ ).
- Produces a sum bit ( $S$ ) and a carry-out bit ( $C_{out}$ ).
- A 4-bit adder is created by cascading four full adders, connecting the $C_{out}$ of one stage to the $C_{in}$ of the next.
Logical Completeness: Any possible truth table can be implemented using only a combination of AND, OR, and NOT gates. This is achieved by identifying input combinations that yield a $1$ and OR-ing the results of those specific AND-gated combinations.

Sequential Logic Circuits are capable of storing information. The output depends on both the current inputs and the sequence of past inputs (the "state").
R-S Latch (Reset-Set):
- $S$ (set) is used to set the value to $1$ .
- $R$ (reset) is used to clear the value to $0$ .
- Quiescent state occurs when $R=1$ and $S=1$ , holding the previous value.
- Setting $R=0$ and $S=1$ resets the output to $0$ . Setting $S=0$ and $R=1$ sets the output to $1$ .
- The state where $R=0$ and $S=0$ is invalid and should be avoided.
Gated D-Latch:
- Features two inputs: Data ( $D$ ) and Write Enable ( $WE$ ).
- When $WE=1$ , the latch stores the value of $D$ .
- When $WE=0$ , the latch retains its previous state regardless of changes to $D$ .
Register:
- A multi-bit storage unit composed of multiple D-latches sharing a common $WE$ signal. When $WE=1$ , an $n$ -bit value is written.
- Multi-bit values are numbered from right (bit $0$ ) to left (bit $n-1$ ). Brackets distinguish ranges, such as $A[14:9]$ .

Memory is organized as a logical array of bits with $k$ locations and $m$ bits per location.
Address Space refers to the number of locations, typically a power of $2$ , denoted as $k = 2^n$ .
Addressability refers to the number of bits stored at each location (e.g., $8$ bits for byte-addressable memory).
Implementation Types:
- Static RAM (SRAM): Fast; retains data as long as power is supplied.
- Dynamic RAM (DRAM): Denser and slower; data decays and must be periodically refreshed.
- Non-volatile Memory: ROM, PROM, and Flash (retain data without power).
A logical memory structure includes an address decoder, word select lines, and write enable ( $WE$ ) controls.

A Finite State Machine (FSM) is a system defined by a finite number of states, inputs, and outputs.
The system transitions between states based on an explicit specification (state diagram) triggered by inputs.
The State of a system is a snapshot of all relevant elements at a specific moment. For example, a basketball scoreboard captures the points, time, and possession.
Clock Circuits: Often used to trigger transitions. At the start of each clock cycle, the machine evaluates its current state and external inputs to move to the next state.
Master-Slave Flipflop:
- A pair of gated D-latches used to store state bits while isolating the next state from the current state.
- Clock Cycle Phase 1: The current state is sent to the logic circuit.
- Clock Cycle Phase 2: The next state computed by the logic is stored in the latch.

The Data Path of a computer, such as the LC-3, integrates both combinational and sequential logic to process information.
Combinational components in the Data Path:
- Decoders: Convert instructions into control signals.
- Multiplexers: Select specific data inputs and outputs.
- Arithmetic Logic Unit (ALU): Performs data operations.
Sequential components in the Data Path:
- State Machine: Coordinates the timing of data movement and control signals.
- Registers and Latches: Provide internal storage elements for the processor.