Introduction to Operating Systems and Computer System Overview

Computer System Architecture and Ecosystem

  • A computer system operates as an ecosystem comprising four principal interacting components:

    • Hardware: Provides basic computing resources, including the central processing unit (CPU), memory, and input/output (I/O) devices.
    • Operating System (OS): Controls and coordinates the utilization of hardware among diverse application programs and users.
    • Application Programs: Define how system resources are deployed to solve specific user computing problems. Examples include word processors, compilers, web browsers, database systems, and video games.
    • Users: Consists of people, mechanical devices, and other computer systems interacting with the machine.

  • Typical Personal Computer (PC) Hardware Architecture:

    • The central processing unit (CPU), disk controller (handling disk drives), USB controller (handling mouse, keyboard, and printer), and graphics adapter (handling the monitor) connect directly to the system bus.
    • Main memory connects directly to the system bus, allowing all controllers access to shared memory storage.

PC Hardware Components and System Bus Interconnection

Operating System Functions and Objectives

  • An Operating System (OS) is a specialized program functioning as an intermediary between the computer user and computer hardware.

  • Operating System Goals from the User Perspective:

    • Executes user programs and simplifies problem-solving workflows.
    • Ensures the overall computer system is convenient to use.

  • Operating System Goals from the System Perspective:

    • Utilizes computer hardware in an efficient manner.
    • Exploits hardware resources across one or multiple processors.
    • Offers structured system services to users and applications.
    • Manages secondary memory structures and I/O peripheral devices.

Computer System Operation and Device Interconnection

  • Basic Operation Structure:

    • A system contains one or more CPUs alongside multiple device controllers connected via a common bus providing access to shared memory.

  • Device Controllers:

    • Dedicated hardware units in charge of specific device categories (such as disk drives, audio devices, or graphics displays).
    • Maintained with local buffer storage and a dedicated set of special-purpose registers.
    • Responsible for executing data transfers between external physical devices and their local buffer storage.
    • Managed directly by system software through an operating system device driver.

  • Concurrent Execution Model:

    • CPU and individual I/O devices execute concurrently.
    • A device controller initiates data transfer from its peripheral device to its local buffer.
    • Once the transfer operation finishes, the device controller informs the CPU by raising an interrupt signal.

  • Interrupt Definition:

    • A fundamental hardware mechanism enabling an external module or device to notify the CPU that it requires immediate attention.

Structural Hardware Elements and Motherboard Layout

  • Structural Elements of a Computer System:

    • Processor: Controls overall computer operation and performs data processing functions. When a system features a single processor, it is designated as the Central Processing Unit (CPU).
    • Main Memory: Stores executable program code and operational data. It is volatile, meaning data is erased when power shuts off. Also termed real memory or primary memory.
    • I/O Modules: Facilitate data movement between the computer system and its external environment, which includes secondary storage devices (such as disks), communications equipment, and user terminals.
    • System Bus: Physical communication wiring and protocols enabling data transfer among processors, main memory, and I/O modules.

  • Motherboard Components:

    • All primary hardware elements are affixed to a central printed circuit board termed the motherboard.
    • Key motherboard connectors and integrated controllers include:
    • CPU Socket (Socket 939\text{Socket } 939)
    • CPU Fan Connector, CPU Fan Heatsink Mount
    • DIMM Memory Slots (×4\times 4)
    • Super I/O Chip
    • 24-pin24\text{-pin} ATX Power Connector
    • Floppy Drive Connector
    • IDE Connectors (×2\times 2)
    • SATA Connectors (×4\times 4)
    • BIOS Flash Chip in PLCC Socket
    • Southbridge chip (fitted with heatsink)
    • CMOS Backup Battery
    • Integrated graphics processor (fitted with heatsink)
    • PCI Slots (×3\times 3)
    • Integrated audio codec chip
    • Integrated Gigabit Ethernet chip
    • PCI Express Slot
    • Rear Integrated Peripheral Connectors: PS/2 Keyboard and Mouse, Serial Port, Parallel Port, VGA, Firewire/IEEE 1394a, USB (×4\times 4), Ethernet port, and Audio jacks (×6\times 6).

Annotated Computer Motherboard Layout

Processor Internal Registers

  • Memory Data Exchange Registers:

    • Memory Address Register (MAR): Holds the exact memory address for the next read or write operation.
    • Memory Buffer Register (MBR): Contains data to be written directly into memory or stores data newly read from memory.

  • I/O Exchange Registers:

    • I/O Address Register (I/OAR): Specifies the distinct I/O device or port being targeted.
    • I/O Buffer Register (I/OBR): Handles data exchange between an I/O module and the processor.

Memory Organization and Process Execution

  • Memory Module Structure:

    • Composed of a sequential array of locations identified by sequentially numbered integer addresses.
    • Each individual address contains a bit pattern that is interpreted as either an executable instruction or raw data.

  • External Device Buffer Functions:

    • I/O modules contain internal buffer storage to temporarily hold data during transmission, preventing execution stalls caused by speed differentials between external hardware and internal buses.

RAM Memory Stick Hardware Module

  • Instruction Processing Cycle:
    • Programs consist of sequences of instructions loaded into memory.
    • Process execution functions via a fundamental two-step instruction cycle:
    1. Fetch: Processor reads an instruction from memory one at a time.
      • The Program Counter (PC) register holds the address of the next instruction to fetch.
      • The Program Counter automatically increments after each successful fetch operation.
    2. Execute: The processor interprets and performs the operations defined by the fetched instruction.
    • Execution continuously loops between instruction fetch and instruction execution.
    • Program execution halts only under specific conditions:
    • System power is turned off.
    • An unrecoverable hardware or software error occurs.
    • An explicit program instruction designed to halt the processor is encountered.

Instruction Execution Flowchart

Cache Memory Mechanisms

  • Cache Concepts:

    • Caching involves copying information from slower main storage into higher-speed storage media.
    • Main memory itself can be conceptualized as a high-speed cache for long-term secondary storage.

  • Speed Mismatch and Locality:

    • High-speed processors run much faster than main memory circuits.
    • Memory caching compensates for speed disparities, increases operational memory performance, and relies on the principle of locality.
    • Memory cache functions transparently and is invisible to the operating system.

  • Cache Operation Sequence:

    • Cache contains duplicate copies of active main memory portions.
    • During memory reads, the processor checks the cache first.
    • If the requested data block is absent (a cache miss), the memory block containing the needed information is transferred from main memory to cache and forwarded to the processor.
    • Data transfer granularity:
    • Transfer between CPU and Cache: High-speed word transfers.
    • Transfer between Main Memory and Cache: Slower block transfers.

Memory Cache and Word Block Transfer Diagram

  • Disk Cache:
    • A reserved segment of main memory utilized as a buffer for temporary disk read/write storage.
    • Performance benefits:
    • Clustered Disk Writes: Replaces multiple small write requests with fewer large data transfers, reducing processor overhead and optimizing disk efficiency.
    • Temporal Data Retrieval: Frequently accessed write data is read directly from memory-based software cache rather than performing physical disk access.

Interrupt Processing and Control Transfer

  • Purpose of Interrupts:

    • Standard mechanism enabling non-CPU components (such as I/O modules and memory) to interrupt CPU execution sequencing.
    • Primary goal is maximizing processor utilization.
    • Prevents processor idling during long wait times required by slow I/O peripherals (e.g., waiting for printers across thousands or millions of CPU cycles).

  • Transfer of Control Sequence:

    1. Interrupt signals travel from hardware devices to the CPU via system bus connections.
    2. When an interrupt occurs, the CPU suspends current program execution at instruction address ii
    3. Control immediately transfers to a predetermined fixed memory location storing the entry address of the Interrupt Handler or Interrupt Service Routine (ISR).
    4. The Interrupt Handler processes the peripheral request.
    5. Upon completion of the ISR, the CPU restores state and resumes the user program execution at instruction address i+1i+1

Interrupt Control Transfer Sequence Diagram

  • Traps and Exceptions:

    • Software-generated interrupts caused by program execution errors (e.g., division by zero) or deliberate user request system calls.
    • The operating system operates inherently as an interrupt-driven software framework.

  • Interrupt Timeline:

    • User program execution alternates with I/O interrupt processing cycles based on device transfer state changes (idle versus active transferring).

Interrupt State Timeline Diagram

Storage Structure and Hierarchy

  • Storage Categories:

    • Main Memory: Large storage accessible directly by the CPU via random access. Volatile in nature; implemented via Dynamic Random-Access Memory (DRAM).
    • Secondary Storage: Nonvolatile capacity extension for main memory.
    • Mechanical Hard Disk Drives (HDDs): Transfer rates ranging from 80–160 MB/s80\text{--}160\text{ MB/s}; used primarily for bulk or archival storage.
    • SATA Solid-State Drives (SSDs): Transfer speeds around 550 MB/s550\text{ MB/s}.
    • NVMe SSDs: Connect directly via PCIe buses, achieving data rates of 7,000–14,000 MB/s7,000\text{--}14,000\text{ MB/s}.

  • Storage Characteristics Trade-offs:

    • Access Speed vs Cost: Faster access time increases cost per bit.
    • Capacity vs Cost: Larger storage capacity decreases cost per bit.
    • Capacity vs Speed: Larger capacity increases access latency (slower speeds).

  • Storage Hierarchy Levels (From Top/Fastest to Bottom/Slowest):

    • Primary Storage (Volatile):
    • Level 1: Registers
    • Level 2: Cache
    • Level 3: Main Memory
    • Secondary Storage (Nonvolatile):
    • Level 4: Nonvolatile Memory / Solid-State Disk
    • Level 5: Hard-Disk Drives (Magnetic Disk)
    • Tertiary Storage (Nonvolatile):
    • Optical Disks
    • Magnetic Tapes

Storage Hierarchy Pyramid

  • Comprehensive Storage Metrics Table:

    • Level 1 (Registers):
    • Typical Size: <1 KB< 1\text{ KB}
    • Implementation Technology: Custom memory with multiple ports CMOS
    • Access Time: 0.25–0.5 ns0.25\text{--}0.5\text{ ns}
    • Bandwidth: 20,000–100,000 MB/s20,000\text{--}100,000\text{ MB/s}
    • Managed By: Compiler
    • Backed By: Cache
    • Level 2 (Cache):
    • Typical Size: <16 MB< 16\text{ MB}
    • Implementation Technology: On-chip or off-chip CMOS SRAM
    • Access Time: 0.5–25 ns0.5\text{--}25\text{ ns}
    • Bandwidth: 5,000–10,000 MB/s5,000\text{--}10,000\text{ MB/s}
    • Managed By: Hardware
    • Backed By: Main memory
    • Level 3 (Main Memory):
    • Typical Size: <64 GB< 64\text{ GB}
    • Implementation Technology: CMOS SRAM / DRAM
    • Access Time: 80–250 ns80\text{--}250\text{ ns}
    • Bandwidth: 1,000–5,000 MB/s1,000\text{--}5,000\text{ MB/s}
    • Managed By: Operating system
    • Backed By: Disk
    • Level 4 (Solid-State Disk):
    • Typical Size: <1 TB< 1\text{ TB}
    • Implementation Technology: Flash memory
    • Access Time: 25,000–50,000 ns25,000\text{--}50,000\text{ ns}
    • Bandwidth: 500 MB/s500\text{ MB/s}
    • Managed By: Operating system
    • Backed By: Disk
    • Level 5 (Magnetic Disk):
    • Typical Size: <10 TB< 10\text{ TB}
    • Implementation Technology: Magnetic disk
    • Access Time: 5,000,000 ns5,000,000\text{ ns}
    • Bandwidth: 20–150 MB/s20\text{--}150\text{ MB/s}
    • Managed By: Operating system
    • Backed By: Disk or tape

  • Key Hierarchy Trends Moving Downward:

    • Decreasing cost per bit.
    • Increasing storage capacity.
    • Increasing access time latency.
    • Decreasing processor access frequency.
    • Decreasing locality of reference.

  • Secondary Memory Attributes:

    • Includes permanent storage media such as hard disks, removable disks, USB flash drives, cloud storage, and magnetic tape.
    • Nonvolatile auxiliary memory structure.
    • Retains program and data files long-term, and acts as an extension to main memory via virtual memory.

Disassembled Hard Disk Drive Chassis

Advanced Hardware Scaling: Multiprocessor and Clustered Systems

  • Multiprocessor and Multicore Architecture:

    • Modern computing relies on multicore hardware across smartphones, desktops, and enterprise servers.
    • Key advantages of multiprocessor scaling:
    • Increased Throughput: Simultaneous execution of NN processes across NN distinct CPUs.
    • Economy of Scale: Shared power supplies, storage devices, and main memory save costs relative to multiple standalone systems.
    • Increased Reliability: Supports fault tolerance and graceful degradation in performance during hardware failures.

  • Core System Structure:

    • Multicore design places two or more processing units (cores) onto a single silicon die.
    • Each core contains independent processor components, registers, and execution units.
    • Symmetric Multiprocessing (SMP): Multiple CPUs share main memory over a unified bus. Each processor contains dedicated registers and cache structures.
    • Dual-Core CPU Configuration: Cores feature dedicated registers and L1 cache levels, while sharing a unified L2 cache connected directly to main memory.

Symmetric Multiprocessing Architecture Diagram

Dual-Core Silicon Chip Architecture

  • Clustered Systems:
    • Comprises multiple independent computer systems linked together to process workloads collaboratively.
    • Shared storage systems are linked using high-speed Storage-Area Networks (SAN).
    • Delivers high-availability service that remains operational despite individual system node failures.
    • Heavily utilized in High-Performance Computing (HPC).
    • Software applications must be constructed with explicit parallelization structures and often employ a Distributed Lock Manager (DLM) to prevent conflicting file access operations.