Detailed Notes on Asynchronous Inputs, Glitches, and PLDs

Asynchronous Inputs:
Inputs that do not synchronize with the system clock (SYSCLK).

  • Example: In a digital system where a START signal changes, if this change occurs close to the setup and hold times of a flip-flop, it can lead to unexpected states in the circuit. For instance, if a signal changes before the clock edge when data is expected to be latched, it can cause erroneous data to be captured.

Output Glitches:
Output glitches occur during state transitions where outputs may temporarily change incorrectly, leading to unreliable digital behavior.

  • An example can be seen in the transition when a flip-flop toggles; due to propagation delays, not all parts of the circuitry may respond in unison, causing a brief incorrect output state.

Modified Example: 4-Bit Binary Serial Adder

  • Binary Counting Order:

    • States assigned as (00, 01, 10, 11) corresponding to inputs a, b, c, d, which implies that as the clock progresses, the system transitions through these states seamlessly.

  • Key Outputs:

    • The output for bit 1 can be defined as:
      D1 = Q1Q0' + Q1'Q0 + ST imes Q0

    • The output for bit 0 can be defined as:
      D0 = ST imes (Q1'Q0') + ST imes (Q1Q0) + C4 imes (Q1Q0')

    • The DONE signal, indicating the completion of the addition, is defined as:
      DONE = Q1'Q0'

    • State machine outputs (S11) are directly influenced by transitions in Q0, highlighting how specific input changes can propagate through the state machine and affect the final output.

Solutions for Glitches

  • Synchronizing Inputs:

    • Synchronizing asynchronous signals like the START signal to prevent violations of setup and hold times is crucial. For instance, if a signal is known to transition at unpredictable intervals, buffering this single signal to align with the system clock can introduce a clock cycle delay but ultimately results in more stable performance by avoiding state violations.

  • State Assignment:

    • Prefer state transitions that minimize changes, ideally changing one bit at a time to prevent glitches, thereby simplifying how signals are propagated. For example, a cyclic sequence is beneficial compared to an arbitrary sequence that flips multiple bits simultaneously.

    • Using Karnaugh Maps (K-Maps) for effective grouping can help optimize state assignments, ensuring minimized transitions between states and promoting smoother operations.

Output Glitch Analysis

  • Observing Output Glitches:

    • Consider the transition from states b='01' to c='10', where during the switch, you may observe a glitch where the outputs do not represent the correct state due to the level of interference from signal propagation delays. This necessitates careful design in the output logic to reduce error possibilities.

  • Stabilizing Outputs:

    • Synchronizing output signals is critical for avoiding intermediate states that don’t reflect actual circuit states. Utilizing a form of latching or ensure outputs are only visible during valid state conditions is important to maintain the integrity of data and outputs.

Read Only Memory (ROM)

  • Definition:
    Stores data permanently, even when powered off, structured as n address bits and m data bits, allowing for long-term storage and retrieval.

  • Example: For n=3, you can store different Boolean functions, such as truth tables, allowing you to directly use stored results in processing without recalculation.

Implementing Boolean Functions Using ROMs:

  • Boolean functions can be stored using truth tables, where each output value corresponds to a specific input combination. For example, you might implement the function
    f(X,Y,Z) = X'Y + YZ' + XZ
    using ROM configurations defined by how truth values align with each function output.

Programmable Logic Devices (PLDs) and FPGAs

  • Types of PLDs:

    • Programmable Logic Array (PLA): A general programmable architecture that provides both AND and OR structures, suitable for a wide range of applications.

    • Programmable Array Logic (PAL): A constrained but faster alternative to PLAs, providing quicker configurations for specific use cases.

    • Field Programmable Gate Arrays (FPGA): Highly flexible chips that allow for reconfigurable operations post-manufacturing, making them ideal for complex design requirements that may evolve over time.

  • FPGA Architecture:

    • An FPGA consists of Configurable Logic Blocks (CLBs), Input/Output Blocks (IOBs), and programmable interconnects for implementing various functions necessary for digital designs.

  • Design Flow:

    • The process usually involves VHDL design, synthesis, simulation, and generation of configuration files for programming the FPGA, highlighting the critical steps necessary to leverage these devices effectively in modern digital designs.

Configuration of FPGAs

  • Look-Up Tables (LUTs):

    • LUTs play a vital role in implementing logic functions wherein each LUT can manage logic functions based on 4 input variables, facilitating diverse operations.

  • Usage of SRAM in LUTs:

    • SRAM is used within LUTs to store configurations necessary for the LUTs to execute specific logic functions, providing a significant advantage in flexibility and operation efficiency, ensuring high-speed operations in various applications.

Conclusion
The strategies for addressing asynchronous inputs and output glitches are essential for ensuring the reliable design of digital circuits. By implementing best practices in state assignments and leveraging the capabilities of programmable logic devices (PLDs) and FPGAs, designers can significantly enhance the robustness and efficiency of their systems