Computer Architecture: Instruction Sets and Instruction Set Design

Instruction set design impacts the performance and functionality of all modern computers.
It provides foundational knowledge to understand the differences between instruction sets and their impact on performance and CPU design.
It reinforces understanding of control units and the relationships between instruction sets and control unit designs.
It provides practical skills in assembly code programming, enabling understanding of what instructions actually do and how they work.
It facilitates writing Assembler for any arbitrary machine architecture by understanding how instructions work.

A register in a CPU typically uses two control signals:
- One signal latches a value from the CPU bus into the register.
- The other asserts the contents of the register on the CPU bus.
Therefore, only two bits in the microword are required to control this register.
Typically, only one source device and one destination device can be used on such a bus.

An “instruction set” is the set of possible instruction types which a given CPU can perform.
An “instruction set” imposes specific constraints upon the internal architecture of a CPU.
Particular hardware and organization are required for particular types of instruction, e.g., an ADD instruction requires an adder.
There is no “right” or “correct” instruction set.
There are many different formats.
Examples of classes of “instruction set” are CISC, RISC, and VLIW.

Consider the high-level code:

Main() {
    a = 1;
    b = a * 2 + b;
}

In a Simple RISC architecture, this might translate to:
```
LDI #1
STA 101
LDA 101
SHL
ADA 102
STA 102
```
In a CISC architecture, the same high-level code might translate to:
```
MOV #1, 101
MOV 101, R1
MUL R1, #2
ADD R1, 102
```
The effect of different instruction sets impacts:
- Hardware
- Ideology
- Performance

The first part of any instruction is typically the “opcode,” which identifies the type of instruction.
The latter part of the instruction contains arguments specific to the opcode, e.g.:
- A memory address (LDA, STA, ADD, SUB, JMP)
- An immediate value (ADDI)
The opcode is typically at the beginning to allow the control unit to quickly determine the instruction type.

The opcode is in a fixed position to allow the control unit to quickly determine the instruction type.

T4: Accumulator -> Memory Write Register
T5: Instruction Register -> CPU Bus; CPU Bus -> Memory Address Register
T6: Memory Address Register -> Address Bus; Memory Write Register -> Data Bus; Control Signal -> Control Bus

The address is held in the operand field.
Must be known at compile time.
T4: Instruction Register -> CPU Bus; CPU Bus -> Program Counter
This is a simple unconditional jump instruction. The PC is reloaded, and the next instruction is fetched from the new point in the program.
If the jump target is not known at compile time, a different approach is needed.

The return address is stored in the Accumulator.
The accumulator must be saved before it is used in the subroutine.
More complex Call instructions are usually implemented using a call stack.
T4: Program Counter -> CPU Bus; CPU Bus -> Accumulator
T5: Instruction Register -> CPU Bus; CPU Bus -> Program Counter
The previous PC value must be saved before the new one is loaded; otherwise, the thread of execution is lost.

Each instruction requires a specific sequence of control signals, each of which must be asserted at the appropriate time to control a specific portion of the CPU.
Microcode is specific to the particular hardware in the CPU.
Typically, microcode for one CPU cannot be reused in another.
Similar CPUs may use modified variants of the same microcode.

Each instruction can be divided into several phases, some of which may be common to many instructions.
Every instruction must begin by fetching the instruction itself, from the address in the PC.
Once this is performed, the instruction register contains the instruction, and it may be decoded (after t3).
In a microcoded machine, decoding is typically performed by using the opcode to locate the microprogram in the control store.
The