Computer-System Structures and Architecture

Computer System Architecture and Operation

• Computer-System Structures overview covers:

  • Computer system operation

  • Input/Output (I/O) structure

  • Storage structure

  • Storage hierarchy

  • Hardware protection

  • General system structure

• Core components of computer system architecture:

  • Central Processing Unit (CPU)

  • Disk controller managing one or more physical disks

  • USB controller interfacing with human interface and output devices including mouse, keyboard, and printer (configured on-line)

  • Graphics adapter interfacing with the monitor display

  • Shared main memory

  • Common system bus connecting the CPU, memory, and individual device controllers to provide access to shared memory

• Operational dynamics between CPU and device controllers:

  • I/O devices and the CPU execute concurrently within the system.

  • Each device controller is dedicated to and in charge of a specific device type.

  • Each device controller maintains its own local buffer storage.

  • Each device controller type has a corresponding operating system device driver designed to manage its functions.

  • The CPU is responsible for moving data between main memory and the local buffers of the controllers (moving data from/to main memory to/from local buffers).

  • I/O operations take place strictly between the peripheral device and the local buffer of the device controller.

  • Upon completing its assigned operation, the device controller informs the CPU by generating an interrupt.

Computer Startup and Bootstrapping

• Bootstrap Program execution:

  • The bootstrap program is the initial code executed when a computer powers up or reboots.

  • Storage medium: Typically stored in Read-Only Memory (ROM) or Erasable Programmable Read-Only Memory (EPROM), commonly classified as firmware or the Basic Input/Output System (BIOS).

  • Operational responsibilities:

  • Initializes all hardware states, including CPU registers, device controllers, and physical memory.

  • Locates and loads the operating system kernel into main memory.

  • Transfers execution control to the operating system kernel.

• Transition to event-driven execution:

  • Once loaded, the operating system kernel begins execution.

  • The operating system starts system daemons, which are background system services provided outside of the kernel proper.

  • After startup completes, the operating system sits idle, waiting for events to occur.

  • The occurrence of any event is communicated to the operating system exclusively through an interrupt.

Interrupt Mechanisms and Handling Architecture

• Classification of interrupts:

  • Operating systems are fundamentally interrupt driven.

  • Interrupts originate from either hardware sources or software sources.

  • Hardware interrupts: Created when a hardware device sends an electrical signal to the CPU across the system bus.

  • Software interrupts: Created when running software executes a designated operation known as a system call (also called a monitor call).

  • Traps (or exceptions): A software-generated interrupt triggered either by an execution error (such as a division by zero error) or by a specific request from a user program for operating system intervention.

  • Additional process issues handled via interrupt mechanisms include infinite loops, processes attempting unauthorized modification of other processes, or processes attempting to overwrite operating system code.

• Interrupt functions and execution control:

  • An interrupt halts current execution and transfers control to a specific interrupt service routine (ISR).

  • Control transfer is generally mediated through an interrupt vector, which is a dispatch table containing the memory addresses of all individual interrupt service routines.

  • The interrupt hardware architecture must save the return address of the interrupted instruction to ensure seamless resumption after servicing.

  • Incoming interrupts are disabled while another interrupt is actively being processed in order to prevent a lost interrupt condition.

• State preservation and identification:

  • The operating system preserves the exact operating state of the CPU by saving all register contents and the program counter ($PC$).

  • The system determines which specific type of interrupt has occurred via:

  • Polling: Sequentially interrogating individual devices to detect which device signaled the interrupt.

  • Vectored interrupt system: Hardware directly provides the index/address of the handling routine via the interrupt vector.

  • Separate, dedicated segments of code determine the precise action required for each distinct category of interrupt.

Input/Output (I/O) Structure and Direct Memory Access (DMA)

• Synchronous I/O processing:

  • Execution control returns to the user program only upon full completion of the initiated I/O operation.

  • The system executes a wait instruction that idles the CPU until the next interrupt arrives.

  • Alternatively, the system enters a wait loop, producing contention for memory access.

  • At most one I/O request can remain outstanding at any time, eliminating simultaneous I/O execution.

• Asynchronous I/O processing:

  • Execution control returns to the user program immediately without waiting for the I/O operation to finish.

  • Programs issue a system call to explicitly request that the operating system allow the user to wait for I/O completion if synchronization becomes necessary.

  • The operating system tracks ongoing operations using a device-status table:

  • Contains a distinct entry for every physical I/O device detailing its type, address, and current operational state.

  • The operating system indexes into the I/O device table to assess device status and modifies the table entry to record incoming interrupts.

• Direct Memory Access (DMA) structure:

  • Employed for high-speed I/O devices capable of moving data at throughput rates close to memory speeds.

  • The device controller transfers entire blocks of data directly between its buffer storage and main memory without continuous CPU intervention.

  • The device controller generates only one interrupt per block transferred, rather than triggering an interrupt for every individual byte (or word).

• von Neumann architecture organization with DMA:

  • The CPU ($*N$) executes a thread of execution.

  • Instructions and data pass between the CPU cache and main memory via instruction execution cycles and data movement paths.

  • The CPU issues I/O requests to the device ($*M$).

  • The device communicates data and interrupts directly to the CPU.

  • Direct Memory Access (DMA) establishes an autonomous, direct high-speed data transmission channel between the device ($*M$) and main memory.

Storage Hierarchy and Caching

• Storage media classification:

  • Main memory: The only large storage medium that the CPU can address and execute directly. Characterized as random access and typically volatile.

  • Secondary storage: Serves as an extension of main memory, providing large nonvolatile storage capacity.

  • Hard-disk drives: Constructed from rigid metal or glass platters coated with magnetic recording media.

  • The platter surface is logically partitioned into concentric tracks.

  • Tracks are further subdivided into physical sectors.

  • The disk controller governs the logical and physical interactions between the disk drive hardware and the computer.

  • Solid-state disks (SSDs): Nonvolatile storage constructed from semiconductor technologies. Faster than mechanical hard disks and widely adopted.

• Structural hierarchy of storage devices:

  • Systems organize storage hierarchically based on three fundamental parameters:

  • Speed (access time)

  • Cost

  • Volatility

  • Primary storage (volatile, high speed, high cost, limited capacity):

  • Hardware registers

  • Cache memory

  • Main memory

  • Secondary storage (nonvolatile, moderate speed and cost, high capacity):

  • Nonvolatile memory (solid-state disks)

  • Hard-disk drives

  • Tertiary storage (nonvolatile, lowest speed, lowest cost, massive capacity):

  • Optical disks

  • Magnetic tapes

• Principles and mechanisms of caching:

  • Caching is implemented across multiple levels in computing systems, including hardware, operating systems, and software.

  • Actively used information is copied temporarily from slower, larger storage systems into faster, smaller storage systems.

  • When data is requested, the faster cache is queried first:

  • If the data is present, it is served directly from cache at high speed.

  • If the data is absent, it is retrieved from slower backing storage, copied into the cache, and subsequently accessed.

  • Because cache storage capacity is significantly smaller than the backing storage being cached, cache management represents an essential system design challenge.

  • Fundamental design parameters include cache sizing and replacement policies.

  • Main memory serves conceptually as a high-speed cache for secondary storage systems.

Performance Metrics and Storage Migration

• Quantitative performance comparison of storage levels:

  • Level 1 — Registers:

  • Typical capacity: $< 1\,\text{KB}$

  • Implementation technology: Custom memory with multiple ports using Complementary Metal–Oxide–Semiconductor (CMOS)

  • Access time: $0.25 - 0.5\,\text{ns}$

  • Bandwidth: $20{,}000 - 100{,}000\,\text{MB/sec}$

  • Managed by: Compiler

  • Backed by: Cache

  • Level 2 — Cache:

  • Typical capacity: $< 16\,\text{MB}$

  • Implementation technology: On-chip or off-chip CMOS Static Random-Access Memory (CMOS SRAM)

  • Access time: $0.5 - 25\,\text{ns}$

  • Bandwidth: $5{,}000 - 10{,}000\,\text{MB/sec}$

  • Managed by: Hardware

  • Backed by: Main memory

  • Level 3 — Main Memory:

  • Typical capacity: $< 64\,\text{GB}$

  • Implementation technology: CMOS SRAM

  • Access time: $80 - 250\,\text{ns}$

  • Bandwidth: $1{,}000 - 5{,}000\,\text{MB/sec}$

  • Managed by: Operating system

  • Backed by: Disk

  • Level 4 — Solid State Disk:

  • Typical capacity: $< 1\,\text{TB}$

  • Implementation technology: Flash memory

  • Access time: $25{,}000 - 50{,}000\,\text{ns}$

  • Bandwidth: $500\,\text{MB/sec}$

  • Managed by: Operating system

  • Backed by: Disk

  • Level 5 — Magnetic Disk:

  • Typical capacity: $< 10\,\text{TB}$

  • Implementation technology: Magnetic disk platters

  • Access time: $5{,}000{,}000\,\text{ns}$

  • Bandwidth: $20 - 150\,\text{MB/sec}$

  • Managed by: Operating system

  • Backed by: Disk or tape

• Data migration and memory consistency:

  • Data items (e.g., an integer value $A$) migrate upwards through the storage hierarchy: from magnetic disk, into main memory, through the cache, and finally into an active hardware register.

  • In multitasking environments, systems must guarantee that software reads the most recently updated value of $A$, irrespective of which hierarchical tier currently stores it.

  • In multiprocessor environments, hardware must enforce cache coherency across all processing units so that every independent CPU cache reflects identical, up-to-date values.

Computer-System Architectures: Multiprocessor and Clustered Systems

• Processor architecture classifications:

  • Single-processor systems: Utilize one general-purpose CPU executing instructions, typically accompanied by dedicated special-purpose processors (such as disk or graphics controllers).

  • Multiprocessor systems (parallel or tightly-coupled systems): Incorporate two or more processors in close communication, sharing the computer bus, system clock, memory, and peripheral devices.

• Primary advantages of multiprocessor systems:

  • 1. Increased throughput: Completes a greater volume of computation in less time (sublinear scaling due to resource contention).

  • 2. Economy of scale: Shared mass storage, memory, and peripheral equipment decrease overall per-processor infrastructure costs.

  • 3. Increased reliability: Facilitates graceful degradation and fault tolerance; failures in individual processors diminish performance proportionally without triggering catastrophic system-wide failure.

• Architectural models of multiprocessing:

  • Asymmetric Multiprocessing: Each processor is assigned a specific task. A master processor controls the system, dispatching work to subordinate worker processors.

  • Symmetric Multiprocessing (SMP): Each processor performs all tasks within the operating system; all processors operate as peers without a master-slave hierarchy.

• Dual-core and multicore processor structures:

  • Designs incorporate multi-chip packaging and multicore silicon.

  • Systems containing all chips may be packaged inside a chassis containing multiple separate systems.

  • Dual-core layout ($\text{Processor}_0$):

  • Core 0 ($\text{CPU core}_0$) contains dedicated registers and a local Level 1 (L1) cache.

  • Core 1 ($\text{CPU core}_1$) contains dedicated registers and a local Level 1 (L1) cache.

  • Both cores share an on-chip Level 2 (L2) cache.

  • The shared L2 cache interfaces directly with external main memory.

• Clustered systems:

  • Consist of two or more independent computer systems joined together to execute computational tasks collaboratively.

  • Typically share common storage interconnected via a Storage-Area Network (SAN).

  • Implement high-availability services structured to endure node hardware failures:

  • Asymmetric clustering: One machine operates in active mode running applications, while a secondary machine remains in hot-standby mode monitoring server health.

  • Symmetric clustering: Multiple nodes execute applications concurrently while monitoring the health of peer nodes.

  • High-Performance Computing (HPC) clusters:

  • Tailored to execute complex scientific and compute-heavy calculations.

  • Application software must be written to employ parallelization techniques across nodes.

  • Clustered environments often implement a Distributed Lock Manager (DLM) to prevent conflicting write operations and race conditions when multiple nodes access shared storage.

Multiprogramming and Multitasking Operating Systems

• Multiprogramming in batch systems:

  • Designed to maximize processor efficiency, as a single interactive user cannot keep both the CPU and all peripheral I/O devices busy simultaneously.

  • Organizes jobs (code and associated data) so that the CPU is never left without an instruction stream to execute.

  • Retains a subset of total system jobs resident in physical memory concurrently.

  • Selects an executable job from memory via job scheduling algorithms.

  • Whenever the executing job pauses to wait for an external event (such as an I/O operation), the operating system switches CPU execution to another job in memory.

• Multitasking (timesharing) in interactive systems:

  • Functions as a logical extension of multiprogramming principles.

  • The CPU switches among executing jobs at high frequencies, allowing individual users to interact directly with programs while they execute (interactive computing).

  • Imposes a system response time requirement of $< 1\,\text{second}$.

  • Each user program loaded and running in memory constitutes a distinct process.

  • When multiple processes are ready to run simultaneously, CPU scheduling determines the allocation order of processor time slices.

  • If total active processes exceed physical memory capacity, swapping mechanisms move processes between main memory and secondary storage.

  • Virtual memory architectures allow the execution of processes whose memory footprints are not completely loaded into physical memory.

Hardware Protection, Dual-Mode Operation, and Privileged Instructions

• Dual-mode operation architecture:

  • Provides fundamental protection mechanisms enabling the operating system to shield its own kernel code and underlying hardware components from errant or malicious programs.

  • Execution is bifurcated into two discrete modes:

  • User mode

  • Kernel mode (also referred to as supervisor mode, system mode, or privileged mode)

• Hardware mode bit implementation:

  • A hardware flag (mode bit) identifies whether currently executing instructions belong to user code or kernel code.

  • When user application software executes, the mode bit is set to user mode.

  • When operating system kernel code executes, the mode bit is set to kernel mode.

  • Prevention of unauthorized mode switching: User applications cannot arbitrarily manipulate the hardware mode bit to kernel mode.

  • Mode switching workflow: A system call alters the mode bit to kernel mode; upon completing service execution, the kernel returns control to the user program and resets the mode bit back to user mode.

• Privileged instructions:

  • Specific hardware instructions classified as privileged can only be executed while the processor operates in kernel mode.

  • If software attempts to execute a privileged instruction while in user mode, the CPU intercepts the instruction, blocks execution, and raises a trap/exception.

  • Examples of privileged instructions:

  • Modifying memory address mapping configurations

  • Flushing or invalidating the data cache

  • Invalidating Translation Lookaside Buffer (TLB) entries (used by the CPU to optimize virtual memory translation)

  • Loading and reading hardware system registers

  • Changing processor execution modes from kernel mode to user mode

  • Adjusting processor operating voltage and clock frequency

  • Halting the physical processor

  • Resetting the physical processor

  • Executing direct hardware I/O instructions