Processor Fundamentals

Von Neuman Model

The features of Von Neuman Model:

made of a central processing Unit
a processor that access the memory directly.
memories that could store programs as well as data.
programs that are made up of instructions and executed in sequential order.

The processor is made up of; ALU, CU, system clock and IAS (immediate access Store)

Arithmetic Logic Unit (ALU)

Performs logical operations like subtraction, division, multiplication and right/left shifts.

The accumulator is used when carrying out ALU operations.

Control Unit (CU)

It reads an instruction in the memory then interprets it. It sends signals by the control bus to tell each components what to do.

The CU ensures synchronisation of data flow and program instructions throughout the computer.

System Clock

Produces timing signals on the control bus to ensure vital synchronisation. Without system clock, computer will crash.

Immediate Access Store (IAS)

It stores all the data and programs the CPU needs to access. Data held in the backing store is placed into the IAS temporarily since the read/write head in the IAS is much faster than in the backing store. It is also considered as a primary RAM.

Registers

There are general purpose registers and special purpose registers.

General purpose registers holds data frequently accessed by the CPU or that can be used by the programmer when accessing the CPU.

Special purpose registers have a specific functions in the CPU.

E.g of general purpose register is the Accumulator.

E.g of special Purpose register:

Register	Abbreviation	Purpose/function
Current Instruction Register	CIR	stores the current instruction being decoded and executed
Index Register	IX	used when carrying out index addressing operations (assembly code)
Memory Address Register	MAR	stores the address of the memory location currently being read from or written to
Memory Data Register	MDR	stores data which has just been read from memory or data which is about to be written to memory
Program Counter	PC	stores the address where the next instruction to be read can be found
Status Register	SR	contain bits which can be set or cleared depending on the operation

System Buses

Address Bus

Carries address throughout the computer system. It is Unidirectional.

The width of the bus is also important. The greater the width the more addresses can be accessed directly.

Data Bus

Carries data throughout the computer system. It is Bidirectional. Data can be an instruction, an address or a numerical value. The wider the data width the larger the word length can be transported.

Control Bus

Carries control signals from the CPU to all other computer components.

Factors that affect the computer’s performance:

Processor Type
- CISC (Complex Instruction Set Computer)
  - More complex instruction set but slow time of execution
- RISC (Reduced Instruction Set Computer)
  - Simpler instruction set and faster execution, needs more instruction for more complex tasks.
Number of cores
- Increasing the cores can allow multitasking, and parallel processing where more data is processed simultaneously.
Clock speed
- It is the number of clock cycles the processor can execute per second.
- More instruction executed per second.
Bus width
- It is the number of bits that can be transferred simultaneously across a bus.
Cash Memory
- Small and fast memory located close to the CPU and stores frequently accessed data and instructions.

How different ports provide connections:

USB (Universal Serial Bus)
- Can be plugged or unplugged when computer is on.
- Automatic plug-and-play without restarting the computer.
- Data can flow in two direction.
- A lot of devices use this type of port.
- Can deliver power.
HDMI (High Definition Multimedia Interface.)
- Designed to transmit high-quality audio and videos between devices.
- Can send audios and videos along the same cable.
- No signal degradation
VGA (Video Graphic Array)
- Similar to HDMI but an older version of it.

Fetch-Execute Cycle.

1	The Program Counter (PC) holds the address of the next instruction to fetch	PC
2	The address from the PC is copied to the Memory Address Register (MAR)	PC → MAR
3	The CPU sends a READ signal to memory via the control bus	Control Bus
4	The instruction at the address in MAR is retrieved from RAM	RAM → MDR
5	The instruction is placed in the Memory Data Register (MDR)	MDR
6	The instruction is copied from MDR to the Current Instruction Register (CIR)	MDR → CIR
7	The PC is incremented to point to the next instruction	PC ← PC + 1

Interrupts

It is defined as a signal that is sent to the processor to temporarily suspend its current task and transfer control to a special routine called Interrupt Service Routine(ISR) to handle the event and return back to its original task.

1. Interrupt Request	Device sends interrupt signal to CPU	Signal via interrupt request (IRQ) line
2. Interrupt Detection	CPU checks for interrupts at end of each fetch-execute cycle	After executing current instruction
3. Save Context	CPU saves current state to stack	Saves: PC (return address), CIR, registers, condition flags
4. Acknowledge	CPU sends acknowledgement to device	Tells device "I'm handling your interrupt"
5. Identify Source	CPU determines which device caused interrupt	Uses Interrupt Vector Table
6. Jump to ISR	CPU loads address of Interrupt Service Routine into PC	PC ← ISR address
7. Execute ISR	CPU runs the ISR to handle the interrupt	Processes the event (e.g., reads keyboard data)
8. Return	CPU restores saved state and resumes interrupted program	PC ← saved address, registers restored

Diagram: Interrupt Handling

text

┌─────────────────────────────────────────────────────────────────────┐
│                     NORMAL PROGRAM EXECUTION                       │
│                                                                     │
│  Instruction 1  →  Instruction 2  →  Instruction 3  →  Instruction 4│
│                                                                     │
└────────────────────────────────┬────────────────────────────────────┘
                                 │
                                 ▼
                    ┌─────────────────────┐
                    │   INTERRUPT OCCURS   │  (e.g., keyboard key pressed)
                    └─────────┬───────────┘
                              │
                              ▼
                    ┌─────────────────────┐
                    │  1. SAVE CONTEXT    │  (PC, registers, flags to stack)
                    └─────────┬───────────┘
                              │
                              ▼
                    ┌─────────────────────┐
                    │  2. IDENTIFY SOURCE │  (Check Interrupt Vector Table)
                    └─────────┬───────────┘
                              │
                              ▼
                    ┌─────────────────────┐
                    │  3. JUMP TO ISR     │  (PC ← ISR address)
                    └─────────┬───────────┘
                              │
                              ▼
                    ┌─────────────────────┐
                    │  4. EXECUTE ISR     │  (Handle keyboard input)
                    └─────────┬───────────┘
                              │
                              ▼
                    ┌─────────────────────┐
                    │  5. RESTORE CONTEXT │  (Registers, flags restored)
                    └─────────┬───────────┘
                              │
                              ▼
┌─────────────────────────────────────────────────────────────────────┐
│                     RESUME PROGRAM EXECUTION                       │
│                                                                     │
│  Instruction 5  →  Instruction 6  →  Instruction 7                 │
│                                                                     │
└─────────────────────────────────────────────────────────────────────┘