Serial Data Transfer Notes

Serial data transfer involves transmitting data one bit at a time over a single data line, in contrast to parallel data transfer, which sends multiple bits simultaneously.

Reduced Signal Skew and Crosstalk: Less susceptible to signal skew and crosstalk due to the fewer electrical wires involved, enabling support for higher frequency clocking.
Reliable Over Longer Distances: Capable of transferring data reliably over longer distances.
Cost-Effective: Lower cost due to the need for fewer wires and connectors.

Lower Data Transfer Rate: For the same clock rate, the data transfer rate is lower compared to parallel interfaces because only one data line is available.
Complex Hardware Interface Design: Requires more complex hardware to handle serial-to-parallel conversion, as processors typically operate on bytes or multiple bytes.

Data transfer occurs in both directions, but transmission and reception are mutually exclusive.
Devices can act as both transmitter and receiver, but not simultaneously.
Requires one data line.
*Diagram:
Tx/Rx Rx/Tx GND GND

Simultaneous data transfer in both directions is possible.
Separate data lines are used for each direction, allowing devices to transmit and receive data concurrently.
*Requires two data lines.
*Diagram:
Rx Tx Tx Rx GND GND

Requires a common clock signal between the transmitter and receiver for synchronization.
The receiver uses the clock signal to latch data at specific intervals (e.g., rising edge of the clock).
Often implemented in a master-slave configuration, where the master provides the clock signal.
Allows for potentially faster transfer rates due to the absence of data overhead for synchronization.
*Diagram:
CLK_Out CLK_In Tx Rx GND GND

Does not use a common clock signal; devices must agree on a pre-fixed clock frequency.
Synchronization is achieved by sending synchronization information over the data line.
Special SYNC words indicate the START/STOP conditions of data packets.
The receiver uses its local clock to track timing after receiving the START SYNC word.
Prone to clock skew issues between the transmitter and receiver clocks.
Diagram:
Tx Rx GND GND

Synchronous serial communication relies on a common clock signal for synchronization, while asynchronous communication does not.
In asynchronous communication, devices must agree on a clock rate, and synchronization information is sent over the data line.
Clock skew can be an issue in asynchronous transmission, mitigated by sending SYNC words periodically.

A synchronous serial bus commonly used by processors to interface with peripheral devices.
Uses a master-slave configuration.
To initiate a transfer: The master pulls the Slave Select (SS) pin low, enabling the target SPI slave.
Data transfer: MOSI (Master Out Slave In) and MISO (Master In Slave Out) pins are used for data transmission.
Data is latched on the rising or falling edge of the SCLK (Serial Clock) signal (configurable).
Supports multiple slaves via multiple Slave Select lines.

A widely used asynchronous serial communication protocol.
Employs special SYNC words to indicate START/STOP conditions.
The receiver uses its local clock to track timing after receiving the START SYNC word.
Includes a START bit (logic ‘0’) to alert the receiver, data bits, an optional parity bit for error detection, and a STOP bit (logic ‘1’) to terminate the transmission. *UART symbols and status:
- IDLE state: Logic ‘1’
- START bit: Logic ‘0’
- STOP bit: Logic ‘1’

IDLE State: Data line is at logic '1'.
START Bit: Transmitter sends a logic '0' to alert the receiver, creating a falling edge.
Data Transmission: Data is sent at a frequency known as the baud rate.
Parity Bit (Optional): Used for error detection; can be even, odd, or no parity.
STOP Bit: A logic '1' to terminate the transmission.

Even Parity: The total number of '1's in the data field and parity field should be even. If the receiver detects an odd number of '1's, a parity error is flagged.
Odd Parity: The total number of '1's should be odd. A parity error is flagged if the receiver detects an even number of '1's.
Framing Error: Occurs if the receiver detects a logic '0' instead of '1' at the expected position of the STOP bit.

The receiver monitors the data line for the START bit (falling edge).
The receiver must know the baud rate to sample data bits correctly.
The internal clock of the UART typically runs at a multiple (e.g., 16x) of the baud rate.
Data is sampled close to the middle of each data bit for higher reliability.