Program Counter (PC) and the Fetch/Execute Cycle

The Program Counter (PC) is the address of the next instruction to be fetched and executed.
The PC is the address stored in the control part of the computer (control unit) and is often referred to as the program counter.
The term PC is historical: while it literally means program counter, it denotes the address of the next instruction in sequence.
In most modern computers, instructions are 4 bytes long (one word).
Therefore, the next instruction after the current one is located at memory address PC + 4, i.e., 4 bytes further along in memory.
The PC is used to locate the instruction in memory for the Fetch step of the Fetch/Execute (F/E) Cycle.
The association between memory and instructions: every instruction has an address, which is the address of the memory location of its first byte.
The memory location of the first byte of an instruction is what the PC points to for fetching.
The PC is stored and maintained by the control unit; it is the mechanism that tells the CPU where to fetch the next instruction from memory.
Practical consequence: the PC guides the sequential flow of a program by default, assuming the next instruction is the next in memory order.
Core takeaway: PC provides a simple, linear progression through memory by incrementing by the instruction size after each fetch, unless explicitly modified by control-flow instructions.

Each instruction occupies 4 bytes in current computers (one word).
This means that consecutive instructions are separated by 4-byte boundaries in memory.
Notation: the size of an instruction is $ext{size} = 4 ext{ bytes}$ .
Consequence: the next instruction address is $PC_{ ext{next}} = PC + 4$ .
The address used to fetch an instruction is the memory address of the first byte of that instruction.
Example: If an instruction starts at address $A$ , its bytes are at $A, A+1, A+2, A+3$ and the next instruction starts at $A+4$ .

The Instruction Fetch step transfers the instruction from memory at the address specified by the PC to the decoder part of the control unit.
After the fetch completes, and while the remainder of the cycle processes the current instruction, the system prepares to process the next instruction.
Convention: the system assumes the next instruction is the immediate successor in memory.
Therefore, the PC is updated to point to the next instruction: PC
ightarrow PC{ ext{new}} = PC{ ext{old}} + 4.
This update ensures that when the next Fetch step occurs, the PC points at the new instruction to fetch.
In short: Fetch uses the address in the PC; after fetch, PC is advanced by the instruction size to prepare for the next fetch.

The sequential-series assumption is not always correct for program flow due to branch and jump instructions.
Branch and jump instructions change the PC to alter program flow.
After the control unit prepares for the next instruction in sequence by adding 4 to the PC, the Instruction Execute step of the current branch/jump instruction resets the PC to a new value.
This reset overrides the sequential PC value, causing the next fetch to begin at a different memory location.
The next instruction is fetched from that new memory location on the next cycle of the F/E Cycle.
This mechanism enables loops, conditional execution, and non-linear control flow (e.g., jumping back to a previous section of code or skipping ahead).
Example scenario:
- Suppose $PC = 0x100$ and the current instruction is a conditional branch to $0x130$ if a condition is true.
- The CPU first increments to prepare the next sequential instruction: PC
  ightarrow 0x104.
- During execution, if the condition is true, the PC is reset to the branch target: PC
  ightarrow 0x130.
- The next fetch will then retrieve the instruction at $0x130$ .

The PC is essential for controlling which instruction the CPU fetches next.
By default, the PC provides sequential execution (PC increments by 4 for each instruction).
Branch and Jump instructions override the sequential flow, enabling loops, conditionals, and subroutine calls.
The PC being stored in the control unit highlights its central role in CPU operation and instruction sequencing.
The term PC is deeply embedded in computer hardware terminology (PC boards, processors with PC registers, etc.).
The design principle here reflects a fundamental abstraction: memory addresses locate instructions; the control unit uses the PC to fetch, decode, and execute instructions in the correct order.
Implications for debugging and reliability: incorrect PC values can cause wrong instructions to be executed, infinite loops, or program crashes; thus, correct PC management is critical.
Philosophical/practical note: the PC embodies the idea of deterministic control flow in a machine—every cycle is driven by a precise address pointer to memory.

The PC is the address of the next instruction to fetch.
Instructions are 4 bytes in length; thus, the next instruction address is $PC_{ ext{next}} = PC + 4$ .
The Instruction Fetch step uses the address in the PC to fetch the current instruction into the decoder.
After fetch, the PC is prepared for the next instruction by incrementing by 4: PC
ightarrow PC + 4.
Branch and Jump instructions override the sequential PC value during their Execute phase, setting PC to a new value and enabling non-sequential control flow.
The PC is a foundational construct linking memory addresses to the flow of program execution.

Instruction size: $ext{size} = 4 ext{ bytes}$
Next instruction address (sequential): $PC_{ ext{next}} = PC + 4$
PC update after fetch: PC
ightarrow PC + 4 \text{(sequential flow)}
Branch/Jump override (illustrative): PC
ightarrow ext{target address} during Execution step

In many architectures, the 4-byte instruction size is common; other architectures may use different word sizes, affecting the increment step.
Branching and jumping are universal concepts in CPUs, enabling functions like loops, conditionals, and subroutine calls.
Understanding the PC is foundational for topics such as instruction pipelining (predicting the next instruction) and memory addressing schemes.