Exhaustive Notes on Computer Organization and Architecture (ITC305)

Course Overview and Requirements

• Course Assignment: ITC305 - Computer Organization and Architecture.
• Discipline: Information Technology, 2nd Year, SIES Graduate School of Technology (Autonomous).
• Teaching Scheme (Hrs.):
  • Theory: $03$ hours.
  • Practical: $03$ hours.
  • Tutorial: $03$ hours (Credits assigned).
• Examination Scheme (Theory Marks):
  • Internal Assessment (CIAP): $20$ marks.
  • Internal Sessional Examination (ISE): $20$ marks.
  • Mid-Semester Examination (MSE): $60$ (ESE).
  • Total Semester Marks: $100$.
• Curriculum Modules:
  • Module 1.0: Overview of Computer Architecture & Organization (CO1). Includes basic organization, block level functional units, Evolution of Computers, Von Neumann model, and Performance measures. Covers 8086 microprocessor architecture, pin description, and operating modes.
  • Module 2.0: Programming 8086 (CO2). Includes addressing modes, instruction sets, Assembly Language Programming (loops, strings, procedures, macros).
  • Module 3.0: Processor Organization (CO3). Includes CPU architecture, register organization, instruction cycle, control unit design (hardwired and micro-programmed), and parallel processing (Flynn’s classification, pipelining).
  • Module 4.0: Data Representation and Arithmetic Algorithms (CO4). Includes IEEE 754 floating point representation, Booth's algorithm, and Restoring/Non-Restoring division.
  • Module 5.0: Memory Organization (CO5). Includes RAM, ROM, Memory Hierarchy, Cache Mapping, and Cache Coherency.
  • Module 6.0: I/O Organization (CO6). Includes I/O modules, 8089 processor, DMA, Programmed I/O, and Interrupt-driven I/O.

Fundamental Concepts of Computer Architecture and Organization

• Computer Architecture:
  • Refers to the view of a computer as presented to software designers.
  • Attributes visible to a programmer that have a direct impact on the logical execution of a program.
  • Attributes include: Instruction set, instruction format, operation codes (opcodes), operand types, addressing modes, registers, memory map, I/O map, interrupt assignment, and DMA channel assignment.
• Computer Organization:
  • Refers to the actual implementation of a computer in hardware.
  • Refers to the operational units and their interconnections that realize the architectural specifications.
  • Relationship: Architecture is usually fixed first; then organization is decided. Two computers with the same architecture can have different organizations.
• Definition of a Computer: A general-purpose device that can be programmed to process information and yield meaningful results.
• Basic Components and Workflow:
  • Program: A list of instructions given to the computer.
  • Information Store: Data, images, files, videos.
  • Processing: The computer processes the information store according to program instructions to produce results.
  • System Components:
    • Memory: Stores programs and data; content is destroyed when powered off.
    • Hard Disk: Stores programs and data permanently.
    • CPU: Central Processing Unit (The "Brain").
    • Peripherals: Keyboard, Mouse, Monitor, Printer.
• Philosophical Query: The transcript identifies "Our brilliant brains" as the most intelligent computer.

Functional Units of a Stored-Program Computer

• Central Processing Unit (CPU):
  • Comprised of the Arithmetic Logic Unit (ALU) and the Control Unit.
  • ALU: Performs arithmetic and logical operations. Operands are stored in high-speed registers during processing.
  • Control Unit: Functions as the "nerve center." Fetches and analyzes instructions, issuing control and timing signals to distribute information.
  • Registers: Fast memory with a single location used to temporarily store instructions, data, or addresses. Faster than cache.
• Memory Unit:
  • Primary Storage: Fast memory operating at electronic speeds. Programs must reside here during execution. Organized into groups called "words."
  • Word Length: Typical lengths range from $16$ to $64$ bits.
  • Memory Access Time: Fixed time to reach any location in RAM; ranges from a few nanoseconds ($ns$) to approximately $100\,ns$.
  • Hierarchy: Caches (small, fast, on-chip) → Main memory (largest/slowest primary unit) → Secondary storage (cheaper, large capacity, magnetic/optical disks).
• Input and Output Units:
  • Input: Coded information (e.g., keyboard presses) is translated into binary code.
  • Output: Sends processed results to the outside world (e.g., printers, displays).
  • Peripheral Devices: Electromechanical units consisting of electronic circuits and mechanical assemblies.

Detailed Analysis of Peripheral Devices

• Keyboard: Detects key presses; sends corresponding codes.
• Mouse: GUI-ideal; senses movement coordinates and button presses.
• Printer: Produces readable paper output (Impact, Ink Jet, or Laser). Can reach $10,000$ lines per minute.
• Hard Disk Drive (HDD): High-speed magnetic recording with flying heads.
• Floppy Disk Drive: Becoming obsolete due to CD and Flash memory; records on rotating magnetic surfaces.
• Compact Disc (CD): $700\,MB$ capacity using optical laser technology.
• Digital Versatile Disk (DVD): High-capacity CD variant; up to $17\,GB$.
• Flash Memory (Pen drive): Electrically erasable, portable memory.
• Modem: Links computer to telephone lines for remote communication.
• Others Mentioned: Scanners (converts pictures to data), Plotters (costly graphics output for CAD/CAM), Card Readers/Punches (obsolete), and Web Cameras.

Evolution of Computers and Generations

• Early History: Charles Babbage designed the Difference Engine No. 2 (8,000 parts, 5 tons, 11 feet long). The first complete version was only finished in 2002.
• First Generation (1940-1956): Vacuum Tubes:
  • ENIAC: First completely electronic computer (1947). Built by the U.S. Army using 18,000 vacuum tubes. Performed $5,000$ additions per second. Caused brownouts when turned on.
  • UNIVAC: First commercially available computer.
  • Storage: Magnetic drums.
• Second Generation (1956-1963): Transistors:
  • Transistors replaced vacuum tubes; smaller, faster, cheaper, and more energy-efficient.
  • TRADIC: First transistorized digital computer ($3\,cu\,ft$). Contained 800 transistors and $10,000$ germanium crystal rectifiers.
  • Languages: Binary to High-level (COBOL, FORTRAN) and Assembly.
• Third Generation (1964-1971): Integrated Circuits (IC):
  • Key components: ICs, microprogramming, parallelism, and pipelining.
  • Introduction of Cache and Virtual memory.
  • Interfaced with keyboards and monitors via operating systems.
• Fourth Generation (1971-Present): Microprocessors:
  • Intel 4004 (1971): First single-chip CPU.
  • Intel 8088 (1979): $300,000$ operations per second.
  • Pentium 4 (2000): $1,700,000,000$ operations per second.
  • VLSI (Very Large-Scale Integration): Millions of transistors on one chip.
• Beyond Fourth Generation / AI:
  • Focus on natural language, learning, self-organization, and quantum computation.
  • Development of 3D transistors to overcome power dissipation barriers at $22\,ns$ and $15\,ns$ technology nodes (Silicon On Insulator - SOI).

Moore's Law and Microarchitecture

• Moore's Law: Introduced by Gordon Moore in 1965. Predicted the number of transistors on a chip doubles annually. The rate eventually settled into an exponential growth pattern of about $59\%$ annually.
• Microarchitecture: Refers to the internal organization of CPU resources (Registers, ALU, I/O) and can be hardwired or microcode controlled.
• Multiprocessor: Refers to multiple cores integrated on a single chip to increase system speed.

The von Neumann Model and IAS Structure

• Stored Program Concept: Both data and instructions are stored in a common memory.
• Execution Cycle: Fetch → Decode → Execute.
• Five Major Units: Memory, ALU, Control Unit, Input, and Output.
• IAS Computer Registers:
  • MBR (Memory Buffer Register): Buffer for data going to/from memory.
  • MAR (Memory Address Register): Specifies the physical address for MBR access.
  • IR (Instruction Register): Holds the 8-bit opcode being executed.
  • IBR (Instruction Buffer Register): Temporarily holds the right-hand instruction from a word.
  • PC (Program Counter): Contains the address of the next instruction-pair to fetch.
  • AC & MQ (Accumulator and Multiplier Quotient): Hold operands and results; combined to store 80-bit results (e.g., $40\times40$ multiplication product).
• von Neumann Bottleneck: The limitation caused by a single data path between the CPU and memory. Separation into separate program and data memories is one attempt to resolve this.

Performance Measurement and Processor Types

• Performance Equation:
  • $T = \frac{N \times S}{R}$
  • $T$: Execution time.
  • $N$: Total number of instructions.
  • $S$: Average machine cycles per instruction.
  • $R$: Frequency of the internal clock.
• More Accurate Version:
  • $T = I \times M_{i} \times T\text{-state}(n) \times t$
  • $M_{i}$: Machine cycles for a given instruction.
  • $T\text{-state}$: Clock periods per cycle.
  • $t$: Time for each T-state.
• Optimization Strategies:
  • Reduce N: Use efficient compilers or CISC architectures.
  • Reduce S: Use RISC processors, pipelining, or cache memory.
  • Increase R: Optimize external clocks.
• Performance Tiers:
  • Single-core: Linear performance curve trending toward saturation.
  • Multi-core: Exponential performance curve; multi-threaded. Includes GPUs and designated I/O processors.
  • Heterogeneous Systems: Connectivity between different devices (smartphones/laptops); abundant data parallelism.
• Manual Calculation Example:
  • Instruction set: MOV Acc (8 cycles), ADI B (4 cycles), MOV Acc (8 cycles). $N = 3$.
  • Clock frequency: $20\,MHz$.
  • Sum cycles = $8+4+8 = 20$.
  • $T = \frac{20}{20 \times 10^{6}} = 1\,\mu s$.

Memory Attributes and Cache Performance

• SRAM vs. DRAM:
  • SRAM (Static RAM): High speed ($1\text{-}2\,ns$), high cost, used for Caches.
  • DRAM (Dynamic RAM): Slower ($400\,ns$), cheaper, used for Main Memory.
• Cache Performance Metrics:
  • t_avg: Average access time.
  • Hit Rate (thit): Ideal is $100\%$. Depends on capacity and locality of reference.
  • Miss Penalty: Time to load data from main memory. Trade-off: Increasing block size reduces miss rate but increases miss penalty.
  • Locality of Reference: Temporal (time-based) and Spatial (space-based).
  • 2:1 Rule of Thumb: Miss rate of a 2-way set associative cache of size $N/2$ is roughly equal to a direct-mapped cache of size $N$.

The 8086 Microprocessor Architecture

• Basics: 16-bit CPU, clock rates of $5$, $8$, or $10\,MHz$, 40-pin CERDIP package.
• Internal Divisions:
  • Bus Interface Unit (BIU): Generates 20-bit physical addresses using an internal adder. Includes a 6-byte instruction prefetch queue. Controls communication with external buses.
  • Execution Unit (EU): Contains the 16-bit ALU, general registers (except segment and IP), and the decoding unit.
• Address Calculation:
  • $Physical Address = (Segment Address \times 10H) + Offset Address$
  • Example: Segment = $1005H$, Offset = $5555H$.
  • Calculation: $(10050H) + (5555H) = 155A5H$.
• Memory Segmentation:
  • $1\,MB$ addressable space ($00000H$ to $FFFFFH$).
  • Logically divided into segments of max $64\,KB$.
  • Allows code/data separation and program relocation.
• 16-Bit Flag Register:
  • Condition Flags: S (Sign), Z (Zero), P (Parity), C (Carry), AC (Auxiliary Carry), O (Overflow).
  • Control Flags: T (Trap - for single-stepping), I (Interrupt), D (Direction - for string processing: $0 =$ auto-increment, $1 =$ auto-decrement).

8086 Pin Description and Bus Operation

• Multiplexed Lines:
  • AD15-AD0: Time multiplexed Address/Data bus. Address on T1; Data on T2, T3, Tw, T4.
  • A19-A16 / S6-S3: Multiplexed Address and Status lines. S3/S4 indicate the active segment register.
• Control Signals:
  • BHE / S7: Bus High Enable. Low during T1 to transfer data over higher byte (D15-D8).
  • RD: Active low read signal.
  • READY: Acknowledgment from slow memory/peripherals for data transfer completion.
  • ALE: Address Latch Enable; used to separate address bits from multiplexed lines.
  • MN/MX: Decides between Minimum (single processor) and Maximum (multiprocessor) mode.
• Interrupts:
  • INTR: Level triggered; sampled during the last clock cycle of an instruction.
  • NMI: Non-maskable interrupt; edge-triggered; Type 2 interrupt.
• Maximum Mode Specific Pins:
  • S2, S1, S0: Encoded status lines defining the bus cycle type.
  • LOCK: Prevents other bus masters from gaining control during a critical instruction.
  • QS1, QS0: Queue status (Empty, 1st byte, Empty Queue, or Subsequent byte).
• T-States (Machine Cycle Stages):
  • T1: Address sent on bus; ALE high.
  • T2: Control signals (RD/WR) active; bus direction change.
  • T3: Actual data transfer between CPU and memory/I/O.
  • T4: Cycle completion; signals inactive; bus released.
• Instruction Pipelining: The queue allows fetching the next instruction while the current one is being executed by the EU. BIU initiates a fetch only when at least 2 bytes in the 6-byte queue are empty.