Computer Systems Architecture and Software Engineering Study Guide

Course Curriculum and Academic Structure

  • Curriculum Context and Related Engineering Coursework:

    • Applied Electricity
    • GET 201
    • 101
    • GET 211: 2D + 1D Ademle and Engineering Drawing (Engr. Drawing)
    • Fluid Statistics

  • Software Engineering and Computing Software Modular Structure:

    • Part A: Computer + Computing (Computer Architecture / Compt. Archi)
    • Part B: Algorithm Development
    • Part C: Data Models + Data Structures
    • Part D: Object-Oriented, Structured, and Visual Programming

  • Core Programming Language:

    • C++

  • Assessment and Grading Scheme:

    • Continuous Assessment (C.A.): Evaluated at 40%40\% of the total grade, fulfilled via a Capstone Project.
    • Final Examination: Evaluated at 60%60\% of the total grade.
    • Mid-Modular Assessment: A progress test is administered specifically between the completion of Part A and the commencement of Part B.
    • Testing Administration and Mode: Administered strictly online utilizing an objective "fill in the gaps" question format.

  • Prescribed Academic Textbooks and Reference Resources:

    • Intro to Computing Systems: From Bits and Gates to C/C++ by Yale Patt and Sanjay Patel
    • Digital Design and Computer Architecture (cited as Digital Design and Comp Archi) by Daviel Harrison and Sape
    • Computer Organization and Design: The Hardware/Software Interface (cited as Comp. Organisation and design :- hardware / software interface)
    • Programming Embedded Systems in C and C++ by Anthony Massa

Modern Computer Architecture Fundamentals

  • Primary Hardware Subsystems:
    • Central Processing Unit (CPU): The central hardware computational engine responsible for carrying out instructions.
    • Control Unit (CU): Directs internal operations, interprets instructions, and manages system control signals.
    • Arithmetic Logic Unit (ALU): Performs mathematical calculations and logical evaluations.
    • Dedicated Internal Registers: High-speed storage locations residing directly inside the CPU, including the Program Counter (PC), the Instruction Register (IR), the Memory Address Register (MAR), and general-purpose registers.
    • Main Memory: External system memory (RAM) utilized for the temporary storage of operating program instructions and runtime data.
    • Bus Architecture:
    • Definition and Function: The bus is the dedicated physical communication channel used to transfer information across the computer.
    • Physical Analogy: Functions directly like physical cables running between internal components to route data and control signals between the CPU and Memory.

The Fetch-Decode-Execute (FDE) Instruction Cycle

  • Operational Frequency and Nature:

    • The CPU continuously executes program instructions through an ongoing, repetitive three-step cycle consisting of Fetch, Decode, and Execute (FDE).
    • This foundational cycle runs at extreme speeds, cycling billions of times per second.

  • Step 1: Fetch (Instruction Retrieval):

    • Purpose: The CPU retrieves the next instruction scheduled for execution from system memory.
    • Mechanism and Internal Flow:
    • The Program Counter (PC) holds the specific memory address of the next instruction to be processed.
    • The CPU sends said memory address to the system memory (RAM).
    • The instruction stored at that targeted address in memory is transmitted back to the CPU and loaded into the Instruction Register (IR).
    • The Program Counter (PC) is auto-updated (incremented) to point directly to the memory address of the subsequent instruction.

  • Step 2: Decode (Instruction Interpretation):

    • Purpose: The CPU interprets and figures out what the fetched instruction means and determines the exact operational steps that are required.
    • Mechanism and Internal Flow:
    • The Control Unit (CU) examines and analyzes the specific bit pattern comprising the instruction currently stored in the Instruction Register (IR).
    • The CU identifies the Operations: Defines the functional task to be performed (examples of operations include ADD, JUMP, LOAD, and STOP).
    • The CU identifies the Operands: Determines the inputs or targets of the operation, which comprise raw data or specific memory locations.
    • The CU configures data path orchestration, defining exactly how data should flow internally into and through the CPU.

  • Step 3: Execute (Instruction Processing):

    • Purpose: The CPU performs the actual physical operations dictated by the decoded instruction.
    • Hardware Interfacing: Involves the Memory Address Register (MAR) and execution datapath to carry out the instruction.
    • Core Execution Capabilities:
    • Performing Arithmetic and Logic operations (e.g., ADD, SUBTRACT, AND, OR, etc.).
    • Loading data from main memory into a designated internal CPU register.
    • Storing data from a CPU register back into external memory.
    • Jumping execution flow to a brand-new instruction address (altering sequential program control).
    • Interacting directly with Input/Output (I/O) devices.

Assembly Language Instruction Walkthrough

  • Concrete Assembly Instruction Trace:

    • Load R1, A — Fetches the data value stored at memory location AA and loads it into register R1R1.
    • Load R2, B — Fetches the data value stored at memory location BB and loads it into register R2R2.
    • Add R3, R1, R2 — Adds the contents of register R1R1 to the contents of register R2R2, storing the final calculated result into register R3R3.
    • Store R3, C — Takes the computed value currently held in register R3R3 and writes/stores it into memory location CC.
    • HALT — Ceases CPU execution of the program sequence.

  • Auxiliary Architectural Notes:

    • Hardware-level primitive directives include GET and Store.
    • Operational elements include circuit and system components referenced as App elements, Element L, and fundamental elements for any electrical system.